Module Name: src
Committed By: maxv
Date: Fri Aug 19 18:53:29 UTC 2016
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
KNF so NXR likes it, and some typos
To generate a diff of this commit:
cvs rdiff -u -r1.88 -r1.89 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.88 src/sys/arch/x86/include/specialreg.h:1.89
--- src/sys/arch/x86/include/specialreg.h:1.88 Sat Jul 16 13:47:01 2016
+++ src/sys/arch/x86/include/specialreg.h Fri Aug 19 18:53:29 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.88 2016/07/16 13:47:01 maxv Exp $ */
+/* $NetBSD: specialreg.h,v 1.89 2016/08/19 18:53:29 maxv Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -34,12 +34,12 @@
/*
* Bits in 386 special registers:
*/
-#define CR0_PE 0x00000001 /* Protected mode Enable */
-#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
-#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
-#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
-#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
-#define CR0_PG 0x80000000 /* PaGing enable */
+#define CR0_PE 0x00000001 /* Protected mode Enable */
+#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
+#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
+#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
+#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
+#define CR0_PG 0x80000000 /* PaGing enable */
/*
* Bits in 486 special registers:
@@ -47,8 +47,8 @@
#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
#define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */
#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
-#define CR0_NW 0x20000000 /* Not Write-through */
-#define CR0_CD 0x40000000 /* Cache Disable */
+#define CR0_NW 0x20000000 /* Not Write-through */
+#define CR0_CD 0x40000000 /* Cache Disable */
/*
* Cyrix 486 DLC special registers, accessible as IO ports.
@@ -94,14 +94,14 @@
/*
* Extended Control Register XCR0
*/
-#define XCR0_X87 0x00000001 /* x87 FPU/MMX state */
-#define XCR0_SSE 0x00000002 /* SSE state */
-#define XCR0_YMM_Hi128 0x00000004 /* AVX-256 (ymmn registers) */
-#define XCR0_BNDREGS 0x00000008 /* Memory protection ext bounds */
-#define XCR0_BNDCSR 0x00000010 /* Memory protection ext state */
-#define XCR0_Opmask 0x00000020 /* AVX-512 Opmask */
-#define XCR0_ZMM_Hi256 0x00000040 /* AVX-512 upper 256 bits low regs */
-#define XCR0_Hi16_ZMM 0x00000080 /* AVX-512 512 bits upper registers */
+#define XCR0_X87 0x00000001 /* x87 FPU/MMX state */
+#define XCR0_SSE 0x00000002 /* SSE state */
+#define XCR0_YMM_Hi128 0x00000004 /* AVX-256 (ymmn registers) */
+#define XCR0_BNDREGS 0x00000008 /* Memory protection ext bounds */
+#define XCR0_BNDCSR 0x00000010 /* Memory protection ext state */
+#define XCR0_Opmask 0x00000020 /* AVX-512 Opmask */
+#define XCR0_ZMM_Hi256 0x00000040 /* AVX-512 upper 256 bits low regs */
+#define XCR0_Hi16_ZMM 0x00000080 /* AVX-512 512 bits upper registers */
/*
* Known fpu bits - only these get enabled
@@ -125,38 +125,38 @@
*/
/* Fn00000001 %edx features */
-#define CPUID_FPU 0x00000001 /* processor has an FPU? */
-#define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
-#define CPUID_DE 0x00000004 /* has debugging extension */
-#define CPUID_PSE 0x00000008 /* has 4MB page size extension */
-#define CPUID_TSC 0x00000010 /* has time stamp counter */
-#define CPUID_MSR 0x00000020 /* has mode specific registers */
-#define CPUID_PAE 0x00000040 /* has phys address extension */
-#define CPUID_MCE 0x00000080 /* has machine check exception */
-#define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
-#define CPUID_APIC 0x00000200 /* has enabled APIC */
-#define CPUID_B10 0x00000400 /* reserved, MTRR */
-#define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */
-#define CPUID_MTRR 0x00001000 /* has memory type range register */
-#define CPUID_PGE 0x00002000 /* has page global extension */
-#define CPUID_MCA 0x00004000 /* has machine check architecture */
-#define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
-#define CPUID_PAT 0x00010000 /* Page Attribute Table */
-#define CPUID_PSE36 0x00020000 /* 36-bit PSE */
-#define CPUID_PN 0x00040000 /* processor serial number */
-#define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
-#define CPUID_B20 0x00100000 /* reserved */
-#define CPUID_DS 0x00200000 /* Debug Store */
-#define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
-#define CPUID_MMX 0x00800000 /* MMX supported */
-#define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */
-#define CPUID_SSE 0x02000000 /* streaming SIMD extensions */
-#define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */
-#define CPUID_SS 0x08000000 /* self-snoop */
-#define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */
-#define CPUID_TM 0x20000000 /* thermal monitor (TCC) */
-#define CPUID_IA64 0x40000000 /* IA-64 architecture */
-#define CPUID_SBF 0x80000000 /* signal break on FERR */
+#define CPUID_FPU 0x00000001 /* processor has an FPU? */
+#define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
+#define CPUID_DE 0x00000004 /* has debugging extension */
+#define CPUID_PSE 0x00000008 /* has 4MB page size extension */
+#define CPUID_TSC 0x00000010 /* has time stamp counter */
+#define CPUID_MSR 0x00000020 /* has mode specific registers */
+#define CPUID_PAE 0x00000040 /* has phys address extension */
+#define CPUID_MCE 0x00000080 /* has machine check exception */
+#define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
+#define CPUID_APIC 0x00000200 /* has enabled APIC */
+#define CPUID_B10 0x00000400 /* reserved, MTRR */
+#define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */
+#define CPUID_MTRR 0x00001000 /* has memory type range register */
+#define CPUID_PGE 0x00002000 /* has page global extension */
+#define CPUID_MCA 0x00004000 /* has machine check architecture */
+#define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
+#define CPUID_PAT 0x00010000 /* Page Attribute Table */
+#define CPUID_PSE36 0x00020000 /* 36-bit PSE */
+#define CPUID_PN 0x00040000 /* processor serial number */
+#define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
+#define CPUID_B20 0x00100000 /* reserved */
+#define CPUID_DS 0x00200000 /* Debug Store */
+#define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
+#define CPUID_MMX 0x00800000 /* MMX supported */
+#define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */
+#define CPUID_SSE 0x02000000 /* streaming SIMD extensions */
+#define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */
+#define CPUID_SS 0x08000000 /* self-snoop */
+#define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */
+#define CPUID_TM 0x20000000 /* thermal monitor (TCC) */
+#define CPUID_IA64 0x40000000 /* IA-64 architecture */
+#define CPUID_SBF 0x80000000 /* signal break on FERR */
#define CPUID_FLAGS1 "\20" \
"\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \
@@ -180,38 +180,38 @@
* CPUID "features" bits in Fn00000001 %ecx
*/
-#define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */
-#define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */
-#define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */
-#define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */
-#define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */
-#define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */
-#define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */
-#define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */
-#define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */
+#define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */
+#define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */
+#define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */
+#define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */
+#define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */
+#define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */
+#define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */
+#define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */
+#define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */
#define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */
-#define CPUID2_CID 0x00000400 /* Context ID */
-#define CPUID2_SDBG 0x00000800 /* Silicon Debug */
-#define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */
-#define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */
-#define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */
-#define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */
+#define CPUID2_CID 0x00000400 /* Context ID */
+#define CPUID2_SDBG 0x00000800 /* Silicon Debug */
+#define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */
+#define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */
+#define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */
+#define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */
/* bit 16 unused 0x00010000 */
-#define CPUID2_PCID 0x00020000 /* Process Context ID */
-#define CPUID2_DCA 0x00040000 /* Direct Cache Access */
-#define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */
-#define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */
-#define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */
-#define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */
-#define CPUID2_POPCNT 0x00800000 /* popcount instruction available */
-#define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */
-#define CPUID2_AES 0x02000000 /* AES instructions */
-#define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */
-#define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */
-#define CPUID2_AVX 0x10000000 /* AVX instructions */
-#define CPUID2_F16C 0x20000000 /* half precision conversion */
-#define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */
-#define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */
+#define CPUID2_PCID 0x00020000 /* Process Context ID */
+#define CPUID2_DCA 0x00040000 /* Direct Cache Access */
+#define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */
+#define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */
+#define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */
+#define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */
+#define CPUID2_POPCNT 0x00800000 /* popcount instruction available */
+#define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */
+#define CPUID2_AES 0x02000000 /* AES instructions */
+#define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */
+#define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */
+#define CPUID2_AVX 0x10000000 /* AVX instructions */
+#define CPUID2_F16C 0x20000000 /* half precision conversion */
+#define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */
+#define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */
#define CPUID2_FLAGS1 "\20" \
"\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \
@@ -312,7 +312,7 @@
/*
* Intel Structured Extended Feature leaf Fn0000_0007
* %eax == 0: Subleaf 0
- * %eax: The Maximun input value for supported subleaf.
+ * %eax: The Maximum input value for supported subleaf.
* %ebx: Feature bits.
* %ecx: Feature bits.
*/
@@ -378,11 +378,11 @@
* %ecx == 0: supported features info:
* %eax: Valid bits of lower 32bits of XCR0
* %ebx: Maximum save area size for features enabled in XCR0
- * %ecx: Maximim save area size for all cpu features
+ * %ecx: Maximum save area size for all cpu features
* %edx: Valid bits of upper 32bits of XCR0
*
* %ecx == 1:
- * %eax: Bit 0 => xsaveopt instruction avalaible (sandy bridge onwards)
+ * %eax: Bit 0 => xsaveopt instruction available (sandy bridge onwards)
* %ebx: Save area size for features enabled by XCR0 | IA32_XSS
* %ecx: Valid bits of lower 32bits of IA32_XSS
* %edx: Valid bits of upper 32bits of IA32_XSS
@@ -395,10 +395,10 @@
*/
/* %ecx=1 %eax */
-#define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */
-#define CPUID_PES1_XSAVEC 0x00000002 /* xsavec & compacted XRSTOR */
-#define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */
-#define CPUID_PES1_XSAVES 0x00000008 /* xsaves/xrstors, IA32_XSS */
+#define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */
+#define CPUID_PES1_XSAVEC 0x00000002 /* xsavec & compacted XRSTOR */
+#define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */
+#define CPUID_PES1_XSAVES 0x00000008 /* xsaves/xrstors, IA32_XSS */
#define CPUID_PES1_FLAGS "\20" \
"\1" "XSAVEOPT" "\2" "XSAVEC" "\3" "XGETBV" "\4" "XSAVES"
@@ -406,8 +406,8 @@
/* Intel Fn80000001 extended features - %edx */
#define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */
#define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */
-#define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */
-#define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */
+#define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */
+#define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */
#define CPUID_EM64T 0x20000000 /* Intel EM64T */
#define CPUID_INTEL_EXT_FLAGS "\20" \
@@ -415,11 +415,11 @@
"\34" "RDTSCP" "\36" "EM64T"
/* Intel Fn80000001 extended features - %ecx */
-#define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/
+#define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/
/* 0x00000020 */ /* LZCNT. Same as AMD's CPUID_LZCNT */
-#define CPUID_PREFETCHW 0x00000100 /* PREFETCHW */
+#define CPUID_PREFETCHW 0x00000100 /* PREFETCHW */
-#define CPUID_INTEL_FLAGS4 "\20" \
+#define CPUID_INTEL_FLAGS4 "\20" \
"\1" "LAHF" "\02" "B01" "\03" "B02" \
"\06" "LZCNT" \
"\11" "PREFETCHW"
@@ -504,16 +504,16 @@
"\15" "B12"
/* AMD Fn8000000a %edx features (SVM features) */
-#define CPUID_AMD_SVM_NP 0x00000001
-#define CPUID_AMD_SVM_LbrVirt 0x00000002
-#define CPUID_AMD_SVM_SVML 0x00000004
-#define CPUID_AMD_SVM_NRIPS 0x00000008
-#define CPUID_AMD_SVM_TSCRateCtrl 0x00000010
-#define CPUID_AMD_SVM_VMCBCleanBits 0x00000020
-#define CPUID_AMD_SVM_FlushByASID 0x00000040
-#define CPUID_AMD_SVM_DecodeAssist 0x00000080
-#define CPUID_AMD_SVM_PauseFilter 0x00000400
-#define CPUID_AMD_SVM_FLAGS "\20" \
+#define CPUID_AMD_SVM_NP 0x00000001
+#define CPUID_AMD_SVM_LbrVirt 0x00000002
+#define CPUID_AMD_SVM_SVML 0x00000004
+#define CPUID_AMD_SVM_NRIPS 0x00000008
+#define CPUID_AMD_SVM_TSCRateCtrl 0x00000010
+#define CPUID_AMD_SVM_VMCBCleanBits 0x00000020
+#define CPUID_AMD_SVM_FlushByASID 0x00000040
+#define CPUID_AMD_SVM_DecodeAssist 0x00000080
+#define CPUID_AMD_SVM_PauseFilter 0x00000400
+#define CPUID_AMD_SVM_FLAGS "\20" \
"\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
"\5" "TSCRate" "\6" "VMCBCleanBits" \
"\7" "FlushByASID" "\10" "DecodeAssist" \
@@ -545,18 +545,18 @@
#define MSR_P5_MC_ADDR 0x000 /* P5 only */
#define MSR_P5_MC_TYPE 0x001 /* P5 only */
#define MSR_TSC 0x010
-#define MSR_CESR 0x011 /* P5 only (trap on P6) */
-#define MSR_CTR0 0x012 /* P5 only (trap on P6) */
-#define MSR_CTR1 0x013 /* P5 only (trap on P6) */
+#define MSR_CESR 0x011 /* P5 only (trap on P6) */
+#define MSR_CTR0 0x012 /* P5 only (trap on P6) */
+#define MSR_CTR1 0x013 /* P5 only (trap on P6) */
#define MSR_IA32_PLATFORM_ID 0x017
#define MSR_APICBASE 0x01b
#define MSR_EBL_CR_POWERON 0x02a
#define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */
-#define MSR_TEST_CTL 0x033
+#define MSR_TEST_CTL 0x033
#define MSR_BIOS_UPDT_TRIG 0x079
-#define MSR_BBL_CR_D0 0x088 /* PII+ only */
-#define MSR_BBL_CR_D1 0x089 /* PII+ only */
-#define MSR_BBL_CR_D2 0x08a /* PII+ only */
+#define MSR_BBL_CR_D0 0x088 /* PII+ only */
+#define MSR_BBL_CR_D1 0x089 /* PII+ only */
+#define MSR_BBL_CR_D2 0x08a /* PII+ only */
#define MSR_BIOS_SIGN 0x08b
#define MSR_PERFCTR0 0x0c1
#define MSR_PERFCTR1 0x0c2
@@ -565,15 +565,15 @@
#define MSR_APERF 0x0e8
#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
#define MSR_MTRRcap 0x0fe
-#define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
-#define MSR_BBL_CR_DECC 0x118 /* PII+ only */
-#define MSR_BBL_CR_CTL 0x119 /* PII+ only */
-#define MSR_BBL_CR_TRIG 0x11a /* PII+ only */
-#define MSR_BBL_CR_BUSY 0x11b /* PII+ only */
-#define MSR_BBL_CR_CTR3 0x11e /* PII+ only */
-#define MSR_SYSENTER_CS 0x174 /* PII+ only */
-#define MSR_SYSENTER_ESP 0x175 /* PII+ only */
-#define MSR_SYSENTER_EIP 0x176 /* PII+ only */
+#define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
+#define MSR_BBL_CR_DECC 0x118 /* PII+ only */
+#define MSR_BBL_CR_CTL 0x119 /* PII+ only */
+#define MSR_BBL_CR_TRIG 0x11a /* PII+ only */
+#define MSR_BBL_CR_BUSY 0x11b /* PII+ only */
+#define MSR_BBL_CR_CTR3 0x11e /* PII+ only */
+#define MSR_SYSENTER_CS 0x174 /* PII+ only */
+#define MSR_SYSENTER_ESP 0x175 /* PII+ only */
+#define MSR_SYSENTER_EIP 0x176 /* PII+ only */
#define MSR_MCG_CAP 0x179
#define MSR_MCG_STATUS 0x17a
#define MSR_MCG_CTL 0x17b
@@ -593,50 +593,50 @@
#define MSR_LASTINTFROMIP 0x1dd
#define MSR_LASTINTTOIP 0x1de
#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
-#define MSR_MTRRphysBase0 0x200
-#define MSR_MTRRphysMask0 0x201
-#define MSR_MTRRphysBase1 0x202
-#define MSR_MTRRphysMask1 0x203
-#define MSR_MTRRphysBase2 0x204
-#define MSR_MTRRphysMask2 0x205
-#define MSR_MTRRphysBase3 0x206
-#define MSR_MTRRphysMask3 0x207
-#define MSR_MTRRphysBase4 0x208
-#define MSR_MTRRphysMask4 0x209
-#define MSR_MTRRphysBase5 0x20a
-#define MSR_MTRRphysMask5 0x20b
-#define MSR_MTRRphysBase6 0x20c
-#define MSR_MTRRphysMask6 0x20d
-#define MSR_MTRRphysBase7 0x20e
-#define MSR_MTRRphysMask7 0x20f
-#define MSR_MTRRphysBase8 0x210
-#define MSR_MTRRphysMask8 0x211
-#define MSR_MTRRphysBase9 0x212
-#define MSR_MTRRphysMask9 0x213
-#define MSR_MTRRphysBase10 0x214
-#define MSR_MTRRphysMask10 0x215
-#define MSR_MTRRphysBase11 0x216
-#define MSR_MTRRphysMask11 0x217
-#define MSR_MTRRphysBase12 0x218
-#define MSR_MTRRphysMask12 0x219
-#define MSR_MTRRphysBase13 0x21a
-#define MSR_MTRRphysMask13 0x21b
-#define MSR_MTRRphysBase14 0x21c
-#define MSR_MTRRphysMask14 0x21d
-#define MSR_MTRRphysBase15 0x21e
-#define MSR_MTRRphysMask15 0x21f
-#define MSR_MTRRfix64K_00000 0x250
-#define MSR_MTRRfix16K_80000 0x258
-#define MSR_MTRRfix16K_A0000 0x259
-#define MSR_MTRRfix4K_C0000 0x268
-#define MSR_MTRRfix4K_C8000 0x269
-#define MSR_MTRRfix4K_D0000 0x26a
-#define MSR_MTRRfix4K_D8000 0x26b
-#define MSR_MTRRfix4K_E0000 0x26c
-#define MSR_MTRRfix4K_E8000 0x26d
-#define MSR_MTRRfix4K_F0000 0x26e
-#define MSR_MTRRfix4K_F8000 0x26f
-#define MSR_CR_PAT 0x277
+#define MSR_MTRRphysBase0 0x200
+#define MSR_MTRRphysMask0 0x201
+#define MSR_MTRRphysBase1 0x202
+#define MSR_MTRRphysMask1 0x203
+#define MSR_MTRRphysBase2 0x204
+#define MSR_MTRRphysMask2 0x205
+#define MSR_MTRRphysBase3 0x206
+#define MSR_MTRRphysMask3 0x207
+#define MSR_MTRRphysBase4 0x208
+#define MSR_MTRRphysMask4 0x209
+#define MSR_MTRRphysBase5 0x20a
+#define MSR_MTRRphysMask5 0x20b
+#define MSR_MTRRphysBase6 0x20c
+#define MSR_MTRRphysMask6 0x20d
+#define MSR_MTRRphysBase7 0x20e
+#define MSR_MTRRphysMask7 0x20f
+#define MSR_MTRRphysBase8 0x210
+#define MSR_MTRRphysMask8 0x211
+#define MSR_MTRRphysBase9 0x212
+#define MSR_MTRRphysMask9 0x213
+#define MSR_MTRRphysBase10 0x214
+#define MSR_MTRRphysMask10 0x215
+#define MSR_MTRRphysBase11 0x216
+#define MSR_MTRRphysMask11 0x217
+#define MSR_MTRRphysBase12 0x218
+#define MSR_MTRRphysMask12 0x219
+#define MSR_MTRRphysBase13 0x21a
+#define MSR_MTRRphysMask13 0x21b
+#define MSR_MTRRphysBase14 0x21c
+#define MSR_MTRRphysMask14 0x21d
+#define MSR_MTRRphysBase15 0x21e
+#define MSR_MTRRphysMask15 0x21f
+#define MSR_MTRRfix64K_00000 0x250
+#define MSR_MTRRfix16K_80000 0x258
+#define MSR_MTRRfix16K_A0000 0x259
+#define MSR_MTRRfix4K_C0000 0x268
+#define MSR_MTRRfix4K_C8000 0x269
+#define MSR_MTRRfix4K_D0000 0x26a
+#define MSR_MTRRfix4K_D8000 0x26b
+#define MSR_MTRRfix4K_E0000 0x26c
+#define MSR_MTRRfix4K_E8000 0x26d
+#define MSR_MTRRfix4K_F0000 0x26e
+#define MSR_MTRRfix4K_F8000 0x26f
+#define MSR_CR_PAT 0x277
#define MSR_MTRRdefType 0x2ff
#define MSR_MC0_CTL 0x400
#define MSR_MC0_STATUS 0x401
@@ -675,30 +675,30 @@
/*
* VIA "Eden" MSRs
*/
-#define MSR_VIA_FCR MSR_VIA_ACE
+#define MSR_VIA_FCR MSR_VIA_ACE
/*
* AMD K6/K7 MSRs.
*/
-#define MSR_K6_UWCCR 0xc0000085
-#define MSR_K7_EVNTSEL0 0xc0010000
-#define MSR_K7_EVNTSEL1 0xc0010001
-#define MSR_K7_EVNTSEL2 0xc0010002
-#define MSR_K7_EVNTSEL3 0xc0010003
-#define MSR_K7_PERFCTR0 0xc0010004
-#define MSR_K7_PERFCTR1 0xc0010005
-#define MSR_K7_PERFCTR2 0xc0010006
-#define MSR_K7_PERFCTR3 0xc0010007
+#define MSR_K6_UWCCR 0xc0000085
+#define MSR_K7_EVNTSEL0 0xc0010000
+#define MSR_K7_EVNTSEL1 0xc0010001
+#define MSR_K7_EVNTSEL2 0xc0010002
+#define MSR_K7_EVNTSEL3 0xc0010003
+#define MSR_K7_PERFCTR0 0xc0010004
+#define MSR_K7_PERFCTR1 0xc0010005
+#define MSR_K7_PERFCTR2 0xc0010006
+#define MSR_K7_PERFCTR3 0xc0010007
/*
* AMD K8 (Opteron) MSRs.
*/
-#define MSR_SYSCFG 0xc0000010
+#define MSR_SYSCFG 0xc0000010
#define MSR_EFER 0xc0000080 /* Extended feature enable */
#define EFER_SCE 0x00000001 /* SYSCALL extension */
#define EFER_LME 0x00000100 /* Long Mode Active */
-#define EFER_LMA 0x00000400 /* Long Mode Enabled */
+#define EFER_LMA 0x00000400 /* Long Mode Enabled */
#define EFER_NXE 0x00000800 /* No-Execute Enabled */
#define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */
@@ -712,54 +712,54 @@
#define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */
#define VMCR_DPD 0x00000001 /* Debug port disable */
-#define VMCR_RINIT 0x00000002 /* intercept init */
-#define VMCR_DISA20 0x00000004 /* Disable A20 masking */
-#define VMCR_LOCK 0x00000008 /* SVM Lock */
-#define VMCR_SVMED 0x00000010 /* SVME Disable */
+#define VMCR_RINIT 0x00000002 /* intercept init */
+#define VMCR_DISA20 0x00000004 /* Disable A20 masking */
+#define VMCR_LOCK 0x00000008 /* SVM Lock */
+#define VMCR_SVMED 0x00000010 /* SVME Disable */
#define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */
/*
* These require a 'passcode' for access. See cpufunc.h.
*/
-#define MSR_HWCR 0xc0010015
-#define HWCR_TLBCACHEDIS 0x00000008
-#define HWCR_FFDIS 0x00000040
-
-#define MSR_NB_CFG 0xc001001f
-#define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL
-#define NB_CFG_DISDATMSK 0x0000001000000000ULL
-#define NB_CFG_INITAPICCPUIDLO (1ULL << 54)
-
-#define MSR_LS_CFG 0xc0011020
-#define LS_CFG_DIS_LS2_SQUISH 0x02000000
-
-#define MSR_IC_CFG 0xc0011021
-#define IC_CFG_DIS_SEQ_PREFETCH 0x00000800
-
-#define MSR_DC_CFG 0xc0011022
-#define DC_CFG_DIS_CNV_WC_SSO 0x00000008
-#define DC_CFG_DIS_SMC_CHK_BUF 0x00000400
-#define DC_CFG_ERRATA_261 0x01000000
-
-#define MSR_BU_CFG 0xc0011023
-#define BU_CFG_ERRATA_298 0x0000000000000002ULL
-#define BU_CFG_ERRATA_254 0x0000000000200000ULL
-#define BU_CFG_ERRATA_309 0x0000000000800000ULL
-#define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL
-#define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL
-#define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL
+#define MSR_HWCR 0xc0010015
+#define HWCR_TLBCACHEDIS 0x00000008
+#define HWCR_FFDIS 0x00000040
+
+#define MSR_NB_CFG 0xc001001f
+#define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL
+#define NB_CFG_DISDATMSK 0x0000001000000000ULL
+#define NB_CFG_INITAPICCPUIDLO (1ULL << 54)
+
+#define MSR_LS_CFG 0xc0011020
+#define LS_CFG_DIS_LS2_SQUISH 0x02000000
+
+#define MSR_IC_CFG 0xc0011021
+#define IC_CFG_DIS_SEQ_PREFETCH 0x00000800
+
+#define MSR_DC_CFG 0xc0011022
+#define DC_CFG_DIS_CNV_WC_SSO 0x00000008
+#define DC_CFG_DIS_SMC_CHK_BUF 0x00000400
+#define DC_CFG_ERRATA_261 0x01000000
+
+#define MSR_BU_CFG 0xc0011023
+#define BU_CFG_ERRATA_298 0x0000000000000002ULL
+#define BU_CFG_ERRATA_254 0x0000000000200000ULL
+#define BU_CFG_ERRATA_309 0x0000000000800000ULL
+#define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL
+#define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL
+#define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL
#define MSR_DE_CFG 0xc0011029
-#define DE_CFG_ERRATA_721 0x00000001
+#define DE_CFG_ERRATA_721 0x00000001
/* AMD Family10h MSRs */
-#define MSR_OSVW_ID_LENGTH 0xc0010140
-#define MSR_OSVW_STATUS 0xc0010141
-#define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b
-#define MSR_UCODE_AMD_PATCHLOADER 0xc0010020
+#define MSR_OSVW_ID_LENGTH 0xc0010140
+#define MSR_OSVW_STATUS 0xc0010141
+#define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b
+#define MSR_UCODE_AMD_PATCHLOADER 0xc0010020
/* X86 MSRs */
-#define MSR_RDTSCP_AUX 0xc0000103
+#define MSR_RDTSCP_AUX 0xc0000103
/*
* Constants related to MTRRs
@@ -775,7 +775,7 @@
* NCRx+0: A31-A24 of starting address
* NCRx+1: A23-A16 of starting address
* NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
- *
+ *
* The non-cacheable region's starting address must be aligned to the
* size indicated by the NCR_SIZE_xx field.
*/
@@ -810,7 +810,7 @@
* 686-class: `rdpmc' instruction
* 586-class: `rdmsr' instruction, CESR MSR
*
- * The descriptions of these events are too lenghy to include here.
+ * The descriptions of these events are too lengthy to include here.
* See Appendix A of "Intel Architecture Software Developer's
* Manual, Volume 3: System Programming" for more information.
*/
@@ -820,11 +820,11 @@
* is CTR1.
*/
-#define PMC5_CESR_EVENT 0x003f
-#define PMC5_CESR_OS 0x0040
-#define PMC5_CESR_USR 0x0080
-#define PMC5_CESR_E 0x0100
-#define PMC5_CESR_P 0x0200
+#define PMC5_CESR_EVENT 0x003f
+#define PMC5_CESR_OS 0x0040
+#define PMC5_CESR_USR 0x0080
+#define PMC5_CESR_E 0x0100
+#define PMC5_CESR_P 0x0200
#define PMC5_DATA_READ 0x00
#define PMC5_DATA_WRITE 0x01
@@ -842,8 +842,8 @@
#define PMC5_INST_TLB_MISS 0x0d
#define PMC5_INST_CACHE_MISS 0x0e
#define PMC5_SEGMENT_REG_LOAD 0x0f
-#define PMC5_BRANCHES 0x12
-#define PMC5_BTB_HITS 0x13
+#define PMC5_BRANCHES 0x12
+#define PMC5_BTB_HITS 0x13
#define PMC5_BRANCH_TAKEN 0x14
#define PMC5_PIPELINE_FLUSH 0x15
#define PMC5_INST_EXECUTED 0x16
@@ -869,214 +869,214 @@
* 686-class Event Selector MSR format.
*/
-#define PMC6_EVTSEL_EVENT 0x000000ff
-#define PMC6_EVTSEL_UNIT 0x0000ff00
-#define PMC6_EVTSEL_UNIT_SHIFT 8
-#define PMC6_EVTSEL_USR (1 << 16)
-#define PMC6_EVTSEL_OS (1 << 17)
-#define PMC6_EVTSEL_E (1 << 18)
-#define PMC6_EVTSEL_PC (1 << 19)
-#define PMC6_EVTSEL_INT (1 << 20)
-#define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */
-#define PMC6_EVTSEL_INV (1 << 23)
-#define PMC6_EVTSEL_COUNTER_MASK 0xff000000
-#define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24
+#define PMC6_EVTSEL_EVENT 0x000000ff
+#define PMC6_EVTSEL_UNIT 0x0000ff00
+#define PMC6_EVTSEL_UNIT_SHIFT 8
+#define PMC6_EVTSEL_USR (1 << 16)
+#define PMC6_EVTSEL_OS (1 << 17)
+#define PMC6_EVTSEL_E (1 << 18)
+#define PMC6_EVTSEL_PC (1 << 19)
+#define PMC6_EVTSEL_INT (1 << 20)
+#define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */
+#define PMC6_EVTSEL_INV (1 << 23)
+#define PMC6_EVTSEL_COUNTER_MASK 0xff000000
+#define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24
/* Data Cache Unit */
-#define PMC6_DATA_MEM_REFS 0x43
-#define PMC6_DCU_LINES_IN 0x45
-#define PMC6_DCU_M_LINES_IN 0x46
-#define PMC6_DCU_M_LINES_OUT 0x47
-#define PMC6_DCU_MISS_OUTSTANDING 0x48
+#define PMC6_DATA_MEM_REFS 0x43
+#define PMC6_DCU_LINES_IN 0x45
+#define PMC6_DCU_M_LINES_IN 0x46
+#define PMC6_DCU_M_LINES_OUT 0x47
+#define PMC6_DCU_MISS_OUTSTANDING 0x48
/* Instruction Fetch Unit */
-#define PMC6_IFU_IFETCH 0x80
-#define PMC6_IFU_IFETCH_MISS 0x81
-#define PMC6_ITLB_MISS 0x85
-#define PMC6_IFU_MEM_STALL 0x86
-#define PMC6_ILD_STALL 0x87
+#define PMC6_IFU_IFETCH 0x80
+#define PMC6_IFU_IFETCH_MISS 0x81
+#define PMC6_ITLB_MISS 0x85
+#define PMC6_IFU_MEM_STALL 0x86
+#define PMC6_ILD_STALL 0x87
/* L2 Cache */
-#define PMC6_L2_IFETCH 0x28
-#define PMC6_L2_LD 0x29
-#define PMC6_L2_ST 0x2a
-#define PMC6_L2_LINES_IN 0x24
-#define PMC6_L2_LINES_OUT 0x26
-#define PMC6_L2_M_LINES_INM 0x25
-#define PMC6_L2_M_LINES_OUTM 0x27
-#define PMC6_L2_RQSTS 0x2e
-#define PMC6_L2_ADS 0x21
-#define PMC6_L2_DBUS_BUSY 0x22
-#define PMC6_L2_DBUS_BUSY_RD 0x23
+#define PMC6_L2_IFETCH 0x28
+#define PMC6_L2_LD 0x29
+#define PMC6_L2_ST 0x2a
+#define PMC6_L2_LINES_IN 0x24
+#define PMC6_L2_LINES_OUT 0x26
+#define PMC6_L2_M_LINES_INM 0x25
+#define PMC6_L2_M_LINES_OUTM 0x27
+#define PMC6_L2_RQSTS 0x2e
+#define PMC6_L2_ADS 0x21
+#define PMC6_L2_DBUS_BUSY 0x22
+#define PMC6_L2_DBUS_BUSY_RD 0x23
/* External Bus Logic */
-#define PMC6_BUS_DRDY_CLOCKS 0x62
-#define PMC6_BUS_LOCK_CLOCKS 0x63
-#define PMC6_BUS_REQ_OUTSTANDING 0x60
-#define PMC6_BUS_TRAN_BRD 0x65
-#define PMC6_BUS_TRAN_RFO 0x66
-#define PMC6_BUS_TRANS_WB 0x67
-#define PMC6_BUS_TRAN_IFETCH 0x68
-#define PMC6_BUS_TRAN_INVAL 0x69
-#define PMC6_BUS_TRAN_PWR 0x6a
-#define PMC6_BUS_TRANS_P 0x6b
-#define PMC6_BUS_TRANS_IO 0x6c
-#define PMC6_BUS_TRAN_DEF 0x6d
-#define PMC6_BUS_TRAN_BURST 0x6e
-#define PMC6_BUS_TRAN_ANY 0x70
-#define PMC6_BUS_TRAN_MEM 0x6f
-#define PMC6_BUS_DATA_RCV 0x64
-#define PMC6_BUS_BNR_DRV 0x61
-#define PMC6_BUS_HIT_DRV 0x7a
-#define PMC6_BUS_HITM_DRDV 0x7b
-#define PMC6_BUS_SNOOP_STALL 0x7e
+#define PMC6_BUS_DRDY_CLOCKS 0x62
+#define PMC6_BUS_LOCK_CLOCKS 0x63
+#define PMC6_BUS_REQ_OUTSTANDING 0x60
+#define PMC6_BUS_TRAN_BRD 0x65
+#define PMC6_BUS_TRAN_RFO 0x66
+#define PMC6_BUS_TRANS_WB 0x67
+#define PMC6_BUS_TRAN_IFETCH 0x68
+#define PMC6_BUS_TRAN_INVAL 0x69
+#define PMC6_BUS_TRAN_PWR 0x6a
+#define PMC6_BUS_TRANS_P 0x6b
+#define PMC6_BUS_TRANS_IO 0x6c
+#define PMC6_BUS_TRAN_DEF 0x6d
+#define PMC6_BUS_TRAN_BURST 0x6e
+#define PMC6_BUS_TRAN_ANY 0x70
+#define PMC6_BUS_TRAN_MEM 0x6f
+#define PMC6_BUS_DATA_RCV 0x64
+#define PMC6_BUS_BNR_DRV 0x61
+#define PMC6_BUS_HIT_DRV 0x7a
+#define PMC6_BUS_HITM_DRDV 0x7b
+#define PMC6_BUS_SNOOP_STALL 0x7e
/* Floating Point Unit */
-#define PMC6_FLOPS 0xc1
-#define PMC6_FP_COMP_OPS_EXE 0x10
-#define PMC6_FP_ASSIST 0x11
-#define PMC6_MUL 0x12
-#define PMC6_DIV 0x12
-#define PMC6_CYCLES_DIV_BUSY 0x14
+#define PMC6_FLOPS 0xc1
+#define PMC6_FP_COMP_OPS_EXE 0x10
+#define PMC6_FP_ASSIST 0x11
+#define PMC6_MUL 0x12
+#define PMC6_DIV 0x12
+#define PMC6_CYCLES_DIV_BUSY 0x14
/* Memory Ordering */
-#define PMC6_LD_BLOCKS 0x03
-#define PMC6_SB_DRAINS 0x04
-#define PMC6_MISALIGN_MEM_REF 0x05
-#define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */
-#define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */
+#define PMC6_LD_BLOCKS 0x03
+#define PMC6_SB_DRAINS 0x04
+#define PMC6_MISALIGN_MEM_REF 0x05
+#define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */
+#define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */
/* Instruction Decoding and Retirement */
-#define PMC6_INST_RETIRED 0xc0
-#define PMC6_UOPS_RETIRED 0xc2
-#define PMC6_INST_DECODED 0xd0
-#define PMC6_EMON_KNI_INST_RETIRED 0xd8
-#define PMC6_EMON_KNI_COMP_INST_RET 0xd9
+#define PMC6_INST_RETIRED 0xc0
+#define PMC6_UOPS_RETIRED 0xc2
+#define PMC6_INST_DECODED 0xd0
+#define PMC6_EMON_KNI_INST_RETIRED 0xd8
+#define PMC6_EMON_KNI_COMP_INST_RET 0xd9
/* Interrupts */
-#define PMC6_HW_INT_RX 0xc8
-#define PMC6_CYCLES_INT_MASKED 0xc6
-#define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
+#define PMC6_HW_INT_RX 0xc8
+#define PMC6_CYCLES_INT_MASKED 0xc6
+#define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
/* Branches */
-#define PMC6_BR_INST_RETIRED 0xc4
-#define PMC6_BR_MISS_PRED_RETIRED 0xc5
-#define PMC6_BR_TAKEN_RETIRED 0xc9
-#define PMC6_BR_MISS_PRED_TAKEN_RET 0xca
-#define PMC6_BR_INST_DECODED 0xe0
-#define PMC6_BTB_MISSES 0xe2
-#define PMC6_BR_BOGUS 0xe4
-#define PMC6_BACLEARS 0xe6
+#define PMC6_BR_INST_RETIRED 0xc4
+#define PMC6_BR_MISS_PRED_RETIRED 0xc5
+#define PMC6_BR_TAKEN_RETIRED 0xc9
+#define PMC6_BR_MISS_PRED_TAKEN_RET 0xca
+#define PMC6_BR_INST_DECODED 0xe0
+#define PMC6_BTB_MISSES 0xe2
+#define PMC6_BR_BOGUS 0xe4
+#define PMC6_BACLEARS 0xe6
/* Stalls */
-#define PMC6_RESOURCE_STALLS 0xa2
-#define PMC6_PARTIAL_RAT_STALLS 0xd2
+#define PMC6_RESOURCE_STALLS 0xa2
+#define PMC6_PARTIAL_RAT_STALLS 0xd2
/* Segment Register Loads */
-#define PMC6_SEGMENT_REG_LOADS 0x06
+#define PMC6_SEGMENT_REG_LOADS 0x06
/* Clocks */
-#define PMC6_CPU_CLK_UNHALTED 0x79
+#define PMC6_CPU_CLK_UNHALTED 0x79
/* MMX Unit */
-#define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */
-#define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */
-#define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */
-#define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */
-#define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */
-#define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */
-#define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */
+#define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */
+#define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */
+#define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */
+#define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */
+#define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */
+#define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */
+#define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */
/* Segment Register Renaming */
-#define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */
-#define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */
-#define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */
+#define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */
+#define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */
+#define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */
/*
* AMD K7 Event Selector MSR format.
*/
-#define K7_EVTSEL_EVENT 0x000000ff
-#define K7_EVTSEL_UNIT 0x0000ff00
-#define K7_EVTSEL_UNIT_SHIFT 8
-#define K7_EVTSEL_USR (1 << 16)
-#define K7_EVTSEL_OS (1 << 17)
-#define K7_EVTSEL_E (1 << 18)
-#define K7_EVTSEL_PC (1 << 19)
-#define K7_EVTSEL_INT (1 << 20)
-#define K7_EVTSEL_EN (1 << 22)
-#define K7_EVTSEL_INV (1 << 23)
-#define K7_EVTSEL_COUNTER_MASK 0xff000000
-#define K7_EVTSEL_COUNTER_MASK_SHIFT 24
+#define K7_EVTSEL_EVENT 0x000000ff
+#define K7_EVTSEL_UNIT 0x0000ff00
+#define K7_EVTSEL_UNIT_SHIFT 8
+#define K7_EVTSEL_USR (1 << 16)
+#define K7_EVTSEL_OS (1 << 17)
+#define K7_EVTSEL_E (1 << 18)
+#define K7_EVTSEL_PC (1 << 19)
+#define K7_EVTSEL_INT (1 << 20)
+#define K7_EVTSEL_EN (1 << 22)
+#define K7_EVTSEL_INV (1 << 23)
+#define K7_EVTSEL_COUNTER_MASK 0xff000000
+#define K7_EVTSEL_COUNTER_MASK_SHIFT 24
/* Segment Register Loads */
-#define K7_SEGMENT_REG_LOADS 0x20
+#define K7_SEGMENT_REG_LOADS 0x20
-#define K7_STORES_TO_ACTIVE_INST_STREAM 0x21
+#define K7_STORES_TO_ACTIVE_INST_STREAM 0x21
/* Data Cache Unit */
-#define K7_DATA_CACHE_ACCESS 0x40
-#define K7_DATA_CACHE_MISS 0x41
-#define K7_DATA_CACHE_REFILL 0x42
-#define K7_DATA_CACHE_REFILL_SYSTEM 0x43
-#define K7_DATA_CACHE_WBACK 0x44
-#define K7_L2_DTLB_HIT 0x45
-#define K7_L2_DTLB_MISS 0x46
-#define K7_MISALIGNED_DATA_REF 0x47
-#define K7_SYSTEM_REQUEST 0x64
-#define K7_SYSTEM_REQUEST_TYPE 0x65
-
-#define K7_SNOOP_HIT 0x73
-#define K7_SINGLE_BIT_ECC_ERROR 0x74
-#define K7_CACHE_LINE_INVAL 0x75
-#define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76
-#define K7_L2_REQUEST 0x79
-#define K7_L2_REQUEST_BUSY 0x7a
+#define K7_DATA_CACHE_ACCESS 0x40
+#define K7_DATA_CACHE_MISS 0x41
+#define K7_DATA_CACHE_REFILL 0x42
+#define K7_DATA_CACHE_REFILL_SYSTEM 0x43
+#define K7_DATA_CACHE_WBACK 0x44
+#define K7_L2_DTLB_HIT 0x45
+#define K7_L2_DTLB_MISS 0x46
+#define K7_MISALIGNED_DATA_REF 0x47
+#define K7_SYSTEM_REQUEST 0x64
+#define K7_SYSTEM_REQUEST_TYPE 0x65
+
+#define K7_SNOOP_HIT 0x73
+#define K7_SINGLE_BIT_ECC_ERROR 0x74
+#define K7_CACHE_LINE_INVAL 0x75
+#define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76
+#define K7_L2_REQUEST 0x79
+#define K7_L2_REQUEST_BUSY 0x7a
/* Instruction Fetch Unit */
-#define K7_IFU_IFETCH 0x80
-#define K7_IFU_IFETCH_MISS 0x81
-#define K7_IFU_REFILL_FROM_L2 0x82
-#define K7_IFU_REFILL_FROM_SYSTEM 0x83
-#define K7_ITLB_L1_MISS 0x84
-#define K7_ITLB_L2_MISS 0x85
-#define K7_SNOOP_RESYNC 0x86
-#define K7_IFU_STALL 0x87
+#define K7_IFU_IFETCH 0x80
+#define K7_IFU_IFETCH_MISS 0x81
+#define K7_IFU_REFILL_FROM_L2 0x82
+#define K7_IFU_REFILL_FROM_SYSTEM 0x83
+#define K7_ITLB_L1_MISS 0x84
+#define K7_ITLB_L2_MISS 0x85
+#define K7_SNOOP_RESYNC 0x86
+#define K7_IFU_STALL 0x87
-#define K7_RETURN_STACK_HITS 0x88
-#define K7_RETURN_STACK_OVERFLOW 0x89
+#define K7_RETURN_STACK_HITS 0x88
+#define K7_RETURN_STACK_OVERFLOW 0x89
/* Retired */
-#define K7_RETIRED_INST 0xc0
-#define K7_RETIRED_OPS 0xc1
-#define K7_RETIRED_BRANCHES 0xc2
-#define K7_RETIRED_BRANCH_MISPREDICTED 0xc3
-#define K7_RETIRED_TAKEN_BRANCH 0xc4
-#define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5
-#define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6
-#define K7_RETIRED_RESYNC_BRANCH 0xc7
-#define K7_RETIRED_NEAR_RETURNS 0xc8
-#define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9
-#define K7_RETIRED_INDIRECT_MISPREDICTED 0xca
+#define K7_RETIRED_INST 0xc0
+#define K7_RETIRED_OPS 0xc1
+#define K7_RETIRED_BRANCHES 0xc2
+#define K7_RETIRED_BRANCH_MISPREDICTED 0xc3
+#define K7_RETIRED_TAKEN_BRANCH 0xc4
+#define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5
+#define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6
+#define K7_RETIRED_RESYNC_BRANCH 0xc7
+#define K7_RETIRED_NEAR_RETURNS 0xc8
+#define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9
+#define K7_RETIRED_INDIRECT_MISPREDICTED 0xca
/* Interrupts */
-#define K7_CYCLES_INT_MASKED 0xcd
-#define K7_CYCLES_INT_PENDING_AND_MASKED 0xce
-#define K7_HW_INTR_RECV 0xcf
-
-#define K7_INSTRUCTION_DECODER_EMPTY 0xd0
-#define K7_DISPATCH_STALLS 0xd1
-#define K7_BRANCH_ABORTS_TO_RETIRE 0xd2
-#define K7_SERIALIZE 0xd3
-#define K7_SEGMENT_LOAD_STALL 0xd4
-#define K7_ICU_FULL 0xd5
-#define K7_RESERVATION_STATIONS_FULL 0xd6
-#define K7_FPU_FULL 0xd7
-#define K7_LS_FULL 0xd8
-#define K7_ALL_QUIET_STALL 0xd9
-#define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda
-
-#define K7_BP0_MATCH 0xdc
-#define K7_BP1_MATCH 0xdd
-#define K7_BP2_MATCH 0xde
-#define K7_BP3_MATCH 0xdf
+#define K7_CYCLES_INT_MASKED 0xcd
+#define K7_CYCLES_INT_PENDING_AND_MASKED 0xce
+#define K7_HW_INTR_RECV 0xcf
+
+#define K7_INSTRUCTION_DECODER_EMPTY 0xd0
+#define K7_DISPATCH_STALLS 0xd1
+#define K7_BRANCH_ABORTS_TO_RETIRE 0xd2
+#define K7_SERIALIZE 0xd3
+#define K7_SEGMENT_LOAD_STALL 0xd4
+#define K7_ICU_FULL 0xd5
+#define K7_RESERVATION_STATIONS_FULL 0xd6
+#define K7_FPU_FULL 0xd7
+#define K7_LS_FULL 0xd8
+#define K7_ALL_QUIET_STALL 0xd9
+#define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda
+
+#define K7_BP0_MATCH 0xdc
+#define K7_BP1_MATCH 0xdd
+#define K7_BP2_MATCH 0xde
+#define K7_BP3_MATCH 0xdf
