Module Name: src
Committed By: jdolecek
Date: Sat Oct 8 16:05:32 UTC 2016
Modified Files:
src/sys/dev/ic: nvmereg.h
Log Message:
add defines for dataset management (from NVMe spec rev 1.2)
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/dev/ic/nvmereg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/ic/nvmereg.h
diff -u src/sys/dev/ic/nvmereg.h:1.5 src/sys/dev/ic/nvmereg.h:1.6
--- src/sys/dev/ic/nvmereg.h:1.5 Sat Sep 17 23:59:30 2016
+++ src/sys/dev/ic/nvmereg.h Sat Oct 8 16:05:32 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmereg.h,v 1.5 2016/09/17 23:59:30 jdolecek Exp $ */
+/* $NetBSD: nvmereg.h,v 1.6 2016/10/08 16:05:32 jdolecek Exp $ */
/* $OpenBSD: nvmereg.h,v 1.10 2016/04/14 11:18:32 dlg Exp $ */
/*
@@ -188,10 +188,27 @@ struct nvme_sqe_io {
uint16_t nlb; /* Number of Logical Blocks */
uint16_t ioflags;
-#define NVM_SQE_IO_FUA __BIT(14) /* Force Unit Access (bypass cache) */
#define NVM_SQE_IO_LR __BIT(15) /* Limited Retry */
+#define NVM_SQE_IO_FUA __BIT(14) /* Force Unit Access (bypass cache) */
uint8_t dsm; /* Dataset Management */
+#define NVM_SQE_IO_INCOMP __BIT(7) /* Incompressible */
+#define NVM_SQE_IO_SEQ __BIT(6) /* Sequential request */
+#define NVM_SQE_IO_LAT_MASK __BITS(4, 5) /* Access Latency */
+#define NVM_SQE_IO_LAT_NONE 0 /* Latency: none */
+#define NVM_SQE_IO_LAT_IDLE __BIT(4) /* Latency: idle */
+#define NVM_SQE_IO_LAT_NORMAL __BIT(5) /* Latency: normal */
+#define NVM_SQE_IO_LAT_LOW __BITS(4, 5) /* Latency: low */
+#define NVM_SQE_IO_FREQ_MASK __BITS(0, 3) /* Access Frequency */
+#define NVM_SQE_IO_FREQ_TYPICAL 0x1 /* Typical */
+#define NVM_SQE_IO_FREQ_INFR_INFW 0x2 /* Infrequent read and writes */
+#define NVM_SQE_IO_FREQ_FRR_INFW 0x3 /* Frequent read, inf. writes */
+#define NVM_SQE_IO_FREQ_INFR_FRW 0x4 /* Inf. read, freq. writes */
+#define NVM_SQE_IO_FREQ_FRR_FRW 0x5 /* Freq. read and writes */
+#define NVM_SQE_IO_FREQ_ONCE 0x6 /* One time i/o operation */
+/* Extra Access Frequency bits for read operations */
+#define NVM_SQE_IO_FREQ_SPEC 0x7 /* Speculative read - prefech */
+#define NVM_SQE_IO_FREQ_OVERWRITE 0x8 /* Will be overwritten soon */
uint8_t _reserved2[3];
uint32_t eilbrt; /* Expected Initial Logical Block
