Module Name: src
Committed By: snj
Date: Thu Dec 8 00:15:25 UTC 2016
Modified Files:
src/sys/arch/x86/include [netbsd-7]: cacheinfo.h specialreg.h
src/usr.sbin/cpuctl/arch [netbsd-7]: i386.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1285):
sys/arch/x86/include/cacheinfo.h: revision 1.22
sys/arch/x86/include/specialreg.h: revisions 1.87 and 1.90
usr.sbin/cpuctl/arch/i386.c: revisions 1.72-1.74
Changes for x86's cpuctl(8):
- Add Quark X1000, Xeon E[57] v4, Core i7-69xx Extreme, 7th gen Core,
Denverton, Xeon Phi [357]200, Future Xeon and Future Xeon Phi.
- Add SGX, UMIP, RDPID, SGXLC, AVX512DQ, AVX512BW and AVX512VL bit.
- Fix the bit location of CLFLUSHOPT.
- Add new TLB descriptor 0x64 and 0xc4.
To generate a diff of this commit:
cvs rdiff -u -r1.18.2.2 -r1.18.2.3 src/sys/arch/x86/include/cacheinfo.h
cvs rdiff -u -r1.78.4.4 -r1.78.4.5 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.58.2.5 -r1.58.2.6 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.18.2.2 src/sys/arch/x86/include/cacheinfo.h:1.18.2.3
--- src/sys/arch/x86/include/cacheinfo.h:1.18.2.2 Sun Mar 6 17:49:55 2016
+++ src/sys/arch/x86/include/cacheinfo.h Thu Dec 8 00:15:25 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.18.2.2 2016/03/06 17:49:55 martin Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.18.2.3 2016/12/08 00:15:25 snj Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -234,6 +234,7 @@ __CI_TBL(CAI_DTLB, 0x5c, 0xff, 64,
__CI_TBL(CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
__CI_TBL(CAI_ITLB, 0x61, 0xff, 48, 4 * 1024, NULL), \
__CI_TBL(CAI_L1_1GBDTLB,0x63, 4, 4,1024*1024 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0x64, 4,512, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0x6a, 8, 64, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0x6b, 8,256, 4 * 1024, NULL), \
__CI_TBL(CAI_L2_DTLB2, 0x6c, 8,128, 0, "2M/4M: 128 entries"),\
@@ -252,6 +253,7 @@ __CI_TBL(CAI_DTLB2, 0xc0, 4, 8,
__CI_TBL(CAI_L2_STLB2, 0xc1, 8,1024, 4 * 1024, "4K/2M: 1024 entries"), \
__CI_TBL(CAI_DTLB2, 0xc2, 4, 16, 4 * 1024, "4K/2M: 16 entries"), \
__CI_TBL(CAI_L2_STLB, 0xc3, 6,1536, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB2, 0xc4, 4, 32, 4 * 1024, "2M/4M: 32 entries"), \
__CI_TBL(CAI_L2_STLB, 0xca, 4,512, 4 * 1024, NULL), \
__CI_TBL(CAI_ICACHE, 0x06, 4, 8 * 1024, 32, NULL), \
__CI_TBL(CAI_ICACHE, 0x08, 4, 16 * 1024, 32, NULL), \
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.78.4.4 src/sys/arch/x86/include/specialreg.h:1.78.4.5
--- src/sys/arch/x86/include/specialreg.h:1.78.4.4 Sun Mar 6 17:49:55 2016
+++ src/sys/arch/x86/include/specialreg.h Thu Dec 8 00:15:25 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.78.4.4 2016/03/06 17:49:55 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.78.4.5 2016/12/08 00:15:25 snj Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -318,6 +318,7 @@
/* %ebx */
#define CPUID_SEF_FSGSBASE __BIT(0)
#define CPUID_SEF_TSC_ADJUST __BIT(1)
+#define CPUID_SEF_SGX __BIT(2)
#define CPUID_SEF_BMI1 __BIT(3)
#define CPUID_SEF_HLE __BIT(4)
#define CPUID_SEF_AVX2 __BIT(5)
@@ -332,6 +333,7 @@
#define CPUID_SEF_MPX __BIT(14)
#define CPUID_SEF_PQE __BIT(15)
#define CPUID_SEF_AVX512F __BIT(16)
+#define CPUID_SEF_AVX512DQ __BIT(17)
#define CPUID_SEF_RDSEED __BIT(18)
#define CPUID_SEF_ADX __BIT(19)
#define CPUID_SEF_SMAP __BIT(20)
@@ -341,25 +343,32 @@
#define CPUID_SEF_AVX512ER __BIT(27)
#define CPUID_SEF_AVX512CD __BIT(28)
#define CPUID_SEF_SHA __BIT(29)
+#define CPUID_SEF_AVX512BW __BIT(30)
+#define CPUID_SEF_AVX512VL __BIT(31)
#define CPUID_SEF_FLAGS "\20" \
- "\1" "FSGSBASE" "\2" "TSCADJUST" "\4" "BMI1" \
+ "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \
"\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \
"\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \
"\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \
- "\21" "AVX512F" "\23" "RDSEED" "\24" "ADX" \
- "\25" "SMAP" "\26" "CLFLUSHOPT" \
- "\32" "PT" "\33" "AVX512PF""\34" "AVX512ER" \
- "\35" "AVX512CD""\36" "SHA"
+ "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \
+ "\25" "SMAP" "\30" "CLFLUSHOPT" \
+ "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \
+ "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL"
/* %ecx */
#define CPUID_SEF_PREFETCHWT1 __BIT(0)
+#define CPUID_SEF_UMIP __BIT(2)
#define CPUID_SEF_PKU __BIT(3)
#define CPUID_SEF_OSPKE __BIT(4)
+#define CPUID_SEF_RDPID __BIT(22)
+#define CPUID_SEF_SGXLC __BIT(30)
#define CPUID_SEF_FLAGS1 "\20" \
- "\1" "PREFETCHWT1" "\4" "PKU" \
- "\5" "OSPKE"
+ "\1" "PREFETCHWT1" "\3" "UMIP" "\4" "PKU" \
+ "\5" "OSPKE" \
+ "\27" "RDPID" \
+ "\37" "SGXLC"
/*
* CPUID Processor extended state Enumeration Fn0000000d
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.58.2.5 src/usr.sbin/cpuctl/arch/i386.c:1.58.2.6
--- src/usr.sbin/cpuctl/arch/i386.c:1.58.2.5 Sun Mar 6 17:49:56 2016
+++ src/usr.sbin/cpuctl/arch/i386.c Thu Dec 8 00:15:25 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.58.2.5 2016/03/06 17:49:56 martin Exp $ */
+/* $NetBSD: i386.c,v 1.58.2.6 2016/12/08 00:15:25 snj Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.58.2.5 2016/03/06 17:49:56 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.58.2.6 2016/12/08 00:15:25 snj Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -298,7 +298,7 @@ const struct cpu_cpuid_nameclass i386_cp
"Pentium (P54C)", "Pentium (P24T)",
"Pentium/MMX", "Pentium", 0,
"Pentium (P54C)", "Pentium/MMX (Tillamook)",
- 0, 0, 0, 0, 0, 0, 0,
+ "Quark X1000", 0, 0, 0, 0, 0, 0,
},
"Pentium", /* Default */
NULL,
@@ -368,12 +368,18 @@ const struct cpu_cpuid_nameclass i386_cp
[0x4c] = "Atom X[57]-Z8000 (Airmont)",
[0x4d] = "Atom C2000",
[0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
- [0x4f] = "Future gen Xeon (Broadwell)",
+ [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme",
+ [0x55] = "Future Xeon",
[0x56] = "Xeon D-1500 (Broadwell)",
- [0x57] = "Next gen Xeon Phi",
+ [0x57] = "Xeon Phi [357]200",
[0x5a] = "Atom E3500",
+ [0x5c] = "Next Atom (Goldmont)",
[0x5d] = "Atom X3-C3000 (Silvermont)",
[0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
+ [0x5f] = "Future Atom (Denverton)",
+ [0x85] = "Future Xeon Phi",
+ [0x8e] = "7th gen Core (Kaby Lake)",
+ [0x9e] = "7th gen Core (Kaby Lake)",
},
"Pentium Pro, II or III", /* Default */
NULL,
