Module Name: src Committed By: msaitoh Date: Wed Dec 28 06:57:27 UTC 2016
Modified Files: src/sys/dev/pci: pci_subr.c pcireg.h Log Message: The Power Controller Control bit (PCIE_SLCSR_PCC) in the Slot Control & Status Register is 0 on power on. Print "Power <on|off>" instead of "<on|off>". To generate a diff of this commit: cvs rdiff -u -r1.155 -r1.156 src/sys/dev/pci/pci_subr.c cvs rdiff -u -r1.118 -r1.119 src/sys/dev/pci/pcireg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/dev/pci/pci_subr.c diff -u src/sys/dev/pci/pci_subr.c:1.155 src/sys/dev/pci/pci_subr.c:1.156 --- src/sys/dev/pci/pci_subr.c:1.155 Wed Nov 2 00:39:56 2016 +++ src/sys/dev/pci/pci_subr.c Wed Dec 28 06:57:27 2016 @@ -1,4 +1,4 @@ -/* $NetBSD: pci_subr.c,v 1.155 2016/11/02 00:39:56 pgoyette Exp $ */ +/* $NetBSD: pci_subr.c,v 1.156 2016/12/28 06:57:27 msaitoh Exp $ */ /* * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. @@ -40,7 +40,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.155 2016/11/02 00:39:56 pgoyette Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.156 2016/12/28 06:57:27 msaitoh Exp $"); #ifdef _KERNEL_OPT #include "opt_pci.h" @@ -1798,7 +1798,8 @@ pci_conf_print_pcie_cap(const pcireg_t * printf("off\n"); break; } - onoff("Power Controller Control", reg, PCIE_SLCSR_PCC); + printf(" Power Controller Control: Power %s\n", + reg & PCIE_SLCSR_PCC ? "off" : "on"); onoff("Electromechanical Interlock Control", reg, PCIE_SLCSR_EIC); onoff("Data Link Layer State Changed Enable", reg, Index: src/sys/dev/pci/pcireg.h diff -u src/sys/dev/pci/pcireg.h:1.118 src/sys/dev/pci/pcireg.h:1.119 --- src/sys/dev/pci/pcireg.h:1.118 Tue Dec 27 03:51:55 2016 +++ src/sys/dev/pci/pcireg.h Wed Dec 28 06:57:27 2016 @@ -1,4 +1,4 @@ -/* $NetBSD: pcireg.h,v 1.118 2016/12/27 03:51:55 msaitoh Exp $ */ +/* $NetBSD: pcireg.h,v 1.119 2016/12/28 06:57:27 msaitoh Exp $ */ /* * Copyright (c) 1995, 1996, 1999, 2000 @@ -978,7 +978,10 @@ typedef u_int8_t pci_revision_t; #define PCIE_SLCSR_HPE __BIT(5) /* Hot Plug Interrupt Enable */ #define PCIE_SLCSR_AIC __BITS(7, 6) /* Attention Indicator Control*/ #define PCIE_SLCSR_PIC __BITS(9, 8) /* Power Indicator Control */ -#define PCIE_SLCSR_PCC __BIT(10) /* Power Controller Control */ +#define PCIE_SLCSR_PCC __BIT(10) /* + * Power Controller Control: + * 0: Power on, 1: Power off. + */ #define PCIE_SLCSR_EIC __BIT(11) /* Electromechanical Interlock*/ #define PCIE_SLCSR_DLLSCE __BIT(12) /* DataLinkLayer State Changed*/ #define PCIE_SLCSR_AUTOSPLDIS __BIT(13) /* Auto Slot Power Limit Dis. */ @@ -1779,7 +1782,7 @@ struct pci_rom { /* * Extended capability ID: 0x0014 - * (Reserved for AMD) + * Enhanced Allocation */ /*