Module Name: src
Committed By: kiyohara
Date: Sat Jan 7 16:19:29 UTC 2017
Modified Files:
src/sys/arch/arm/arm: cpufunc_asm_pj4b.S
src/sys/arch/arm/marvell: armadaxp.c armadaxpvar.h files.marvell
kirkwood.c mv78xx0.c mvsoc.c mvsoc_space.c mvsocreg.h mvsocvar.h
orion.c
src/sys/arch/evbarm/armadaxp: armadaxp_machdep.c
src/sys/arch/evbarm/marvell: marvell_machdep.c marvellreg.h
Added Files:
src/sys/arch/arm/marvell: dove.c dovereg.h mvsoc_sdhc.c mvsocpmu.c
mvsocpmuvar.h
Log Message:
Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func,
getclk into that.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/marvell/armadaxp.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/marvell/armadaxpvar.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/marvell/dove.c \
src/sys/arch/arm/marvell/dovereg.h src/sys/arch/arm/marvell/mvsoc_sdhc.c \
src/sys/arch/arm/marvell/mvsocpmu.c \
src/sys/arch/arm/marvell/mvsocpmuvar.h
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/marvell/files.marvell
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/marvell/kirkwood.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/marvell/mv78xx0.c
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/marvell/mvsoc.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/marvell/mvsoc_space.c
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/marvell/mvsocreg.h
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/marvell/mvsocvar.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/marvell/orion.c
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/evbarm/marvell/marvell_machdep.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/evbarm/marvell/marvellreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.12 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.13
--- src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.12 Sat Jan 7 15:22:11 2017
+++ src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Sat Jan 7 16:19:28 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_pj4b.S,v 1.12 2017/01/07 15:22:11 kiyohara Exp $ */
+/* $NetBSD: cpufunc_asm_pj4b.S,v 1.13 2017/01/07 16:19:28 kiyohara Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -102,6 +102,7 @@ ENTRY(pj4b_config)
RET
END(pj4b_config)
+#ifdef AURORA_IO_CACHE_COHERENCY
/* LINTSTUB: void pj4b_io_coherency_barrier(vaddr_t, paddr_t, vsize_t); */
ENTRY_NP(pj4b_io_coherency_barrier)
movw r0, #:lower16:_C_LABEL(armadaxp_l2_barrier_reg)
@@ -120,3 +121,4 @@ END(pj4b_io_coherency_barrier)
STRONG_ALIAS(pj4b_dcache_cfu_wbinv_range, pj4b_io_coherency_barrier)
STRONG_ALIAS(pj4b_dcache_cfu_inv_range, pj4b_io_coherency_barrier)
STRONG_ALIAS(pj4b_dcache_cfu_wb_range, pj4b_io_coherency_barrier)
+#endif
Index: src/sys/arch/arm/marvell/armadaxp.c
diff -u src/sys/arch/arm/marvell/armadaxp.c:1.15 src/sys/arch/arm/marvell/armadaxp.c:1.16
--- src/sys/arch/arm/marvell/armadaxp.c:1.15 Wed Jun 3 02:53:19 2015
+++ src/sys/arch/arm/marvell/armadaxp.c Sat Jan 7 16:19:28 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp.c,v 1.15 2015/06/03 02:53:19 hsuenaga Exp $ */
+/* $NetBSD: armadaxp.c,v 1.16 2017/01/07 16:19:28 kiyohara Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
*******************************************************************************/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.15 2015/06/03 02:53:19 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.16 2017/01/07 16:19:28 kiyohara Exp $");
#define _INTR_PRIVATE
@@ -90,7 +90,6 @@ int iocc_state = 0;
vaddr_t misc_base;
vaddr_t armadaxp_l2_barrier_reg;
-extern void (*mvsoc_intr_init)(void);
static void armadaxp_intr_init(void);
static void armadaxp_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
@@ -111,6 +110,17 @@ static void armadaxp_err_pic_source_name
int, char*, size_t);
static int armadaxp_err_pic_pending_irqs(struct pic_softc *);
+static void armadaxp_getclks(void);
+static void armada370_getclks(void);
+static int armadaxp_clkgating(struct marvell_attach_args *);
+
+static int armadaxp_l2_init(bus_addr_t);
+static paddr_t armadaxp_sdcache_wbalign_base(vaddr_t, paddr_t, psize_t);
+static paddr_t armadaxp_sdcache_wbalign_end(vaddr_t, paddr_t, psize_t);
+#ifdef AURORA_IO_CACHE_COHERENCY
+static void armadaxp_io_coherency_init(void);
+#endif
+
struct vco_freq_ratio {
uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */
uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */
@@ -511,13 +521,13 @@ static struct {
};
/*
- * armadaxp_intr_bootstrap:
+ * armadaxp_bootstrap:
*
- * Initialize the rest of the interrupt subsystem, making it
+ * Initialize the rest of the Armada XP dependencies, making it
* ready to handle interrupts from devices.
*/
void
-armadaxp_intr_bootstrap(bus_addr_t pbase)
+armadaxp_bootstrap(vaddr_t vbase, bus_addr_t pbase)
{
int i;
@@ -534,6 +544,35 @@ armadaxp_intr_bootstrap(bus_addr_t pbase
MPIC_WRITE(ARMADAXP_MLMB_MPIC_ICE, i);
mvsoc_intr_init = armadaxp_intr_init;
+
+ mvsoc_clkgating = armadaxp_clkgating;
+
+ misc_base = vbase + ARMADAXP_MISC_BASE;
+ switch (mvsoc_model()) {
+ case MARVELL_ARMADAXP_MV78130:
+ case MARVELL_ARMADAXP_MV78160:
+ case MARVELL_ARMADAXP_MV78230:
+ case MARVELL_ARMADAXP_MV78260:
+ case MARVELL_ARMADAXP_MV78460:
+ armadaxp_getclks();
+ break;
+
+ case MARVELL_ARMADA370_MV6707:
+ case MARVELL_ARMADA370_MV6710:
+ case MARVELL_ARMADA370_MV6W11:
+ armada370_getclks();
+ break;
+ }
+
+#ifdef L2CACHE_ENABLE
+ /* Initialize L2 Cache */
+ armadaxp_l2_init(pbase);
+#endif
+
+#ifdef AURORA_IO_CACHE_COHERENCY
+ /* Initialize cache coherency */
+ armadaxp_io_coherency_init();
+#endif
}
static void
@@ -744,7 +783,7 @@ armadaxp_err_pic_pending_irqs(struct pic
* Clock functions
*/
-void
+static void
armadaxp_getclks(void)
{
uint64_t sar_reg;
@@ -789,7 +828,7 @@ armadaxp_getclks(void)
curcpu()->ci_data.cpu_cc_freq = mvPclk;
}
-void
+static void
armada370_getclks(void)
{
uint32_t sar;
@@ -834,7 +873,7 @@ armada370_getclks(void)
* L2 Cache initialization
*/
-int
+static int
armadaxp_l2_init(bus_addr_t pbase)
{
u_int32_t reg;
@@ -1030,7 +1069,8 @@ armadaxp_sdcache_wbinv_range(vaddr_t va,
__asm__ __volatile__("dsb");
}
-void
+#ifdef AURORA_IO_CACHE_COHERENCY
+static void
armadaxp_io_coherency_init(void)
{
uint32_t reg;
@@ -1057,8 +1097,9 @@ armadaxp_io_coherency_init(void)
/* Mark as enabled */
iocc_state = 1;
}
+#endif
-int
+static int
armadaxp_clkgating(struct marvell_attach_args *mva)
{
uint32_t val;
Index: src/sys/arch/arm/marvell/armadaxpvar.h
diff -u src/sys/arch/arm/marvell/armadaxpvar.h:1.2 src/sys/arch/arm/marvell/armadaxpvar.h:1.3
--- src/sys/arch/arm/marvell/armadaxpvar.h:1.2 Wed Jun 3 02:53:19 2015
+++ src/sys/arch/arm/marvell/armadaxpvar.h Sat Jan 7 16:19:28 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxpvar.h,v 1.2 2015/06/03 02:53:19 hsuenaga Exp $ */
+/* $NetBSD: armadaxpvar.h,v 1.3 2017/01/07 16:19:28 kiyohara Exp $ */
/*
* Copyright (c) 2015 SUENAGA Hiroki
* All rights reserved.
@@ -29,10 +29,6 @@
#include <arm/marvell/mvsocvar.h>
#include <machine/bus_defs.h>
-/* device initalization */
-extern void armadaxp_io_coherency_init(void);
-extern int armadaxp_l2_init(bus_addr_t);
-
/* l2cache maintanance */
extern void armadaxp_sdcache_inv_all(void);
extern void armadaxp_sdcache_wb_all(void);
Index: src/sys/arch/arm/marvell/files.marvell
diff -u src/sys/arch/arm/marvell/files.marvell:1.17 src/sys/arch/arm/marvell/files.marvell:1.18
--- src/sys/arch/arm/marvell/files.marvell:1.17 Wed Jun 3 04:20:02 2015
+++ src/sys/arch/arm/marvell/files.marvell Sat Jan 7 16:19:28 2017
@@ -1,4 +1,4 @@
-# $NetBSD: files.marvell,v 1.17 2015/06/03 04:20:02 hsuenaga Exp $
+# $NetBSD: files.marvell,v 1.18 2017/01/07 16:19:28 kiyohara Exp $
#
# Configuration info for Marvell System on Chip support
#
@@ -14,7 +14,8 @@ file arch/arm/marvell/mvsoc_dma.c
file arch/arm/arm32/irq_dispatch.S
# Some SoC(ARMADAXP) reports false DeviceID.
-defflag opt_mvsoc.h ORION KIRKWOOD MV78XX0 ARMADAXP
+defflag opt_mvsoc.h ORION KIRKWOOD MV78XX0 DOVE
+ ARMADAXP
MVSOC_CONSOLE_EARLY
defparam opt_mvsoc.h MVSOC_INTERREGS_PBASE
MVSOC_FIXUP_DEVID MEMSIZE
@@ -22,6 +23,7 @@ file arch/arm/marvell/mvsoc_intr.c
file arch/arm/marvell/orion.c orion
file arch/arm/marvell/kirkwood.c kirkwood
file arch/arm/marvell/mv78xx0.c mv78xx0
+file arch/arm/marvell/dove.c dove
file arch/arm/marvell/armadaxp.c armadaxp
@@ -89,11 +91,19 @@ file arch/arm/marvell/mvsocgpp.c mvsocg
# Secure Digital Input/Output (SDIO) Interface
attach mvsdio at mvsoc with mvsdio_mbus
+# Also SDHC (i.e. Dove)
+attach sdhc at mvsoc with mvsoc_sdhc
+file arch/arm/marvell/mvsoc_sdhc.c mvsoc_sdhc
# Thermal Sensor
device mvsocts: sysmon_envsys
attach mvsocts at mvsoc
file arch/arm/marvell/mvsocts.c mvsocts
+# Power Management Unit
+device mvsocpmu: sysmon_envsys
+attach mvsocpmu at mvsoc
+file arch/arm/marvell/mvsocpmu.c mvsocpmu needs-flag
+
# SPI Serial Peripheral Interface
attach mvspi at mvsoc with mvspi_mbus
Index: src/sys/arch/arm/marvell/kirkwood.c
diff -u src/sys/arch/arm/marvell/kirkwood.c:1.9 src/sys/arch/arm/marvell/kirkwood.c:1.10
--- src/sys/arch/arm/marvell/kirkwood.c:1.9 Tue Mar 11 07:52:37 2014
+++ src/sys/arch/arm/marvell/kirkwood.c Sat Jan 7 16:19:28 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: kirkwood.c,v 1.9 2014/03/11 07:52:37 martin Exp $ */
+/* $NetBSD: kirkwood.c,v 1.10 2017/01/07 16:19:28 kiyohara Exp $ */
/*
* Copyright (c) 2010 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: kirkwood.c,v 1.9 2014/03/11 07:52:37 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: kirkwood.c,v 1.10 2017/01/07 16:19:28 kiyohara Exp $");
#define _INTR_PRIVATE
@@ -56,6 +56,9 @@ static void kirkwood_pic_source_name(str
static int kirkwood_find_pending_irqs(void);
+static void kirkwood_getclks(vaddr_t);
+static int kirkwood_clkgating(struct marvell_attach_args *);
+
static const char * const sources[64] = {
"MainHighSum(0)", "Bridge(1)", "Host2CPU DB(2)", "CPU2Host DB(3)",
"Reserved_4(4)", "Xor0Chan0(5)", "Xor0Chan1(6)", "Xor1Chan0(7)",
@@ -111,15 +114,14 @@ static struct {
/*
- * kirkwood_intr_bootstrap:
+ * kirkwood_bootstrap:
*
- * Initialize the rest of the interrupt subsystem, making it
+ * Initialize the rest of the Kirkwood dependencies, making it
* ready to handle interrupts from devices.
*/
void
-kirkwood_intr_bootstrap(void)
+kirkwood_bootstrap(vaddr_t iobase)
{
- extern void (*mvsoc_intr_init)(void);
/* disable all interrupts */
write_mlmbreg(KIRKWOOD_MLMB_MIRQIMLR, 0);
@@ -139,6 +141,9 @@ kirkwood_intr_bootstrap(void)
}
gpp_irqbase = 96; /* Main Low(32) + High(32) + Bridge(32) */
#endif
+
+ kirkwood_getclks(iobase);
+ mvsoc_clkgating = kirkwood_clkgating;
}
static void
@@ -224,8 +229,8 @@ kirkwood_find_pending_irqs(void)
* Clock functions
*/
-void
-kirkwood_getclks(bus_addr_t iobase)
+static void
+kirkwood_getclks(vaddr_t iobase)
{
uint32_t reg;
uint16_t model;
@@ -282,7 +287,7 @@ kirkwood_getclks(bus_addr_t iobase)
}
-int
+static int
kirkwood_clkgating(struct marvell_attach_args *mva)
{
uint32_t val;
Index: src/sys/arch/arm/marvell/mv78xx0.c
diff -u src/sys/arch/arm/marvell/mv78xx0.c:1.1 src/sys/arch/arm/marvell/mv78xx0.c:1.2
--- src/sys/arch/arm/marvell/mv78xx0.c:1.1 Mon Sep 30 13:07:30 2013
+++ src/sys/arch/arm/marvell/mv78xx0.c Sat Jan 7 16:19:28 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: mv78xx0.c,v 1.1 2013/09/30 13:07:30 kiyohara Exp $ */
+/* $NetBSD: mv78xx0.c,v 1.2 2017/01/07 16:19:28 kiyohara Exp $ */
/*
* Copyright (c) 2010 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mv78xx0.c,v 1.1 2013/09/30 13:07:30 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mv78xx0.c,v 1.2 2017/01/07 16:19:28 kiyohara Exp $");
#define _INTR_PRIVATE
@@ -59,6 +59,8 @@ static void mv78xx0_pic_source_name(stru
static int mv78xx0_find_pending_irqs(void);
+static void mv78xx0_getclks(vaddr_t);
+
static const char * const sources[64] = {
"ErrSum(0)", "SPI(1)", "TWSI0(2)", "TWSI1(3)",
"IDMA0(4)", "IDMA1(5)", "IDMA2(6)", "IDMA3(7)",
@@ -93,15 +95,14 @@ static struct pic_softc mv78xx0_pic = {
/*
- * mv78xx0_intr_bootstrap:
+ * mv78xx0_bootstrap:
*
- * Initialize the rest of the interrupt subsystem, making it
+ * Initialize the rest of the Discovery Innovation dependencies, making it
* ready to handle interrupts from devices.
*/
void
-mv78xx0_intr_bootstrap(void)
+mv78xx0_bootstrap(vaddr_t iobase)
{
- extern void (*mvsoc_intr_init)(void);
/* disable all interrupts */
write_mlmbreg(MV78XX0_ICI_IRQIMER, 0);
@@ -113,8 +114,12 @@ mv78xx0_intr_bootstrap(void)
mvsoc_intr_init = mv78xx0_intr_init;
+#if NMVSOCGPP > 0
gpp_npins = 32;
gpp_irqbase = 64; /* Main Low(32) + High(32) */
+#endif
+
+ mv78xx0_getclks(iobase);
}
static void
@@ -197,8 +202,8 @@ mv78xx0_find_pending_irqs(void)
* Clock functions
*/
-void
-mv78xx0_getclks(bus_addr_t iobase)
+static void
+mv78xx0_getclks(vaddr_t iobase)
{
const static int sys2cpu_clk_ratio_m[] = /* Mul constant */
{ 1, 3, 2, 5, 3, 7, 4, 9, 5, 1, 6 };
Index: src/sys/arch/arm/marvell/mvsoc.c
diff -u src/sys/arch/arm/marvell/mvsoc.c:1.24 src/sys/arch/arm/marvell/mvsoc.c:1.25
--- src/sys/arch/arm/marvell/mvsoc.c:1.24 Fri Nov 6 12:54:52 2015
+++ src/sys/arch/arm/marvell/mvsoc.c Sat Jan 7 16:19:28 2017
@@ -1,6 +1,6 @@
-/* $NetBSD: mvsoc.c,v 1.24 2015/11/06 12:54:52 kiyohara Exp $ */
+/* $NetBSD: mvsoc.c,v 1.25 2017/01/07 16:19:28 kiyohara Exp $ */
/*
- * Copyright (c) 2007, 2008, 2013, 2014 KIYOHARA Takashi
+ * Copyright (c) 2007, 2008, 2013, 2014, 2016 KIYOHARA Takashi
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.24 2015/11/06 12:54:52 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.25 2017/01/07 16:19:28 kiyohara Exp $");
#include "opt_cputypes.h"
#include "opt_mvsoc.h"
@@ -52,6 +52,7 @@ __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.
#include <arm/marvell/orionreg.h>
#include <arm/marvell/kirkwoodreg.h>
#include <arm/marvell/mv78xx0reg.h>
+#include <arm/marvell/dovereg.h>
#include <arm/marvell/armadaxpvar.h>
#include <arm/marvell/armadaxpreg.h>
@@ -73,6 +74,7 @@ static int mvsoc_search(device_t, cfdata
static int mvsoc_target_ddr(uint32_t, uint32_t *, uint32_t *);
static int mvsoc_target_ddr3(uint32_t, uint32_t *, uint32_t *);
+static int mvsoc_target_axi(int, uint32_t *, uint32_t *);
static int mvsoc_target_peripheral(uint32_t, uint32_t, uint32_t *, uint32_t *);
uint32_t mvPclk, mvSysclk, mvTclk = 0;
@@ -146,6 +148,11 @@ static struct {
{ MARVELL_TAG_SDRAM_CS3,
MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR },
+ { MARVELL_TAG_AXI_CS0,
+ MARVELL_ATTR_AXI_DDR, MVSOC_UNITID_DDR },
+ { MARVELL_TAG_AXI_CS1,
+ MARVELL_ATTR_AXI_DDR, MVSOC_UNITID_DDR },
+
{ MARVELL_TAG_DDR3_CS0,
MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR },
{ MARVELL_TAG_DDR3_CS1,
@@ -250,6 +257,29 @@ static struct {
MV78XX0_ATTR_CRYPT, MV78XX0_UNITID_CRYPT },
#endif
+#if defined(DOVE)
+ { DOVE_TAG_PEX0_MEM,
+ DOVE_ATTR_PEX_MEM, MVSOC_UNITID_PEX },
+ { DOVE_TAG_PEX0_IO,
+ DOVE_ATTR_PEX_IO, MVSOC_UNITID_PEX },
+ { DOVE_TAG_PEX1_MEM,
+ DOVE_ATTR_PEX_MEM, DOVE_UNITID_PEX1 },
+ { DOVE_TAG_PEX1_IO,
+ DOVE_ATTR_PEX_IO, DOVE_UNITID_PEX1 },
+ { DOVE_TAG_CRYPT,
+ DOVE_ATTR_SA, DOVE_UNITID_SA },
+ { DOVE_TAG_SPI0,
+ DOVE_ATTR_SPI0, MVSOC_UNITID_DEVBUS },
+ { DOVE_TAG_SPI1,
+ DOVE_ATTR_SPI1, MVSOC_UNITID_DEVBUS },
+ { DOVE_TAG_BOOTROM,
+ DOVE_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS },
+ { DOVE_TAG_PMU,
+ DOVE_ATTR_NAND, DOVE_UNITID_NAND },
+ { DOVE_TAG_PMU,
+ DOVE_ATTR_PMU, DOVE_UNITID_PMU },
+#endif
+
#if defined(ARMADAXP)
{ ARMADAXP_TAG_PEX00_MEM,
ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX0 },
@@ -294,6 +324,10 @@ static struct {
#undef MV78XX0
#define MV78XX0(m) MARVELL_MV78XX0_ ## m
#endif
+#if defined(DOVE)
+#undef DOVE
+#define DOVE(m) MARVELL_DOVE_ ## m
+#endif
#if defined(ARMADAXP)
#undef ARMADAXP
#define ARMADAXP(m) MARVELL_ARMADAXP_ ## m
@@ -353,6 +387,16 @@ static struct {
{ MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" },
#endif
+#if defined(DOVE)
+ { DOVE(88AP510), 0, "88AP510", "Z0", "Dove" },
+ { DOVE(88AP510), 1, "88AP510", "Z1", "Dove" },
+ { DOVE(88AP510), 2, "88AP510", "Y0", "Dove" },
+ { DOVE(88AP510), 3, "88AP510", "Y1", "Dove" },
+ { DOVE(88AP510), 4, "88AP510", "X0", "Dove" },
+ { DOVE(88AP510), 6, "88AP510", "A0", "Dove" },
+ { DOVE(88AP510), 7, "88AP510", "A1", "Dove" },
+#endif
+
#if defined(ARMADAXP)
{ ARMADAXP(MV78130), 1, "MV78130", "A0", "Armada XP" },
{ ARMADAXP(MV78160), 1, "MV78160", "A0", "Armada XP" },
@@ -387,6 +431,12 @@ enum marvell_tags ddr3_tags[] = {
MARVELL_TAG_UNDEFINED
};
+enum marvell_tags axi_tags[] = {
+ MARVELL_TAG_AXI_CS0,
+ MARVELL_TAG_AXI_CS1,
+
+ MARVELL_TAG_UNDEFINED
+};
static struct {
uint16_t model;
uint8_t rev;
@@ -439,6 +489,17 @@ static struct {
{ MV78XX0(MV78200), 1, ddr_tags },
#endif
+#if defined(DOVE)
+ { DOVE(88AP510), 0, axi_tags },
+ { DOVE(88AP510), 1, axi_tags },
+ { DOVE(88AP510), 2, axi_tags },
+ { DOVE(88AP510), 3, axi_tags },
+ { DOVE(88AP510), 4, axi_tags },
+ { DOVE(88AP510), 5, axi_tags },
+ { DOVE(88AP510), 6, axi_tags },
+ { DOVE(88AP510), 7, axi_tags },
+#endif
+
#if defined(ARMADAXP)
{ ARMADAXP(MV78130), 1, ddr3_tags },
{ ARMADAXP(MV78160), 1, ddr3_tags },
@@ -667,6 +728,32 @@ static const struct mvsoc_periph {
{ MV78XX0(MV78200), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA },
#endif
+#if defined(DOVE)
+#define DOVE_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ)
+
+ { DOVE(88AP510), "mvsoctmr",0, MVSOC_TMR_BASE, DOVE_IRQ_TMR },
+ { DOVE(88AP510), "mvsocpmu",0, DOVE_PMU_BASE, DOVE_IRQ_PMU },
+ { DOVE(88AP510), "com", 0, MVSOC_COM0_BASE, DOVE_IRQ_UART0 },
+ { DOVE(88AP510), "com", 1, MVSOC_COM1_BASE, DOVE_IRQ_UART1 },
+ { DOVE(88AP510), "com", 2, DOVE_COM2_BASE, DOVE_IRQ_UART2 },
+ { DOVE(88AP510), "com", 3, DOVE_COM3_BASE, DOVE_IRQ_UART3 },
+ { DOVE(88AP510), "gttwsi", 0, MVSOC_TWSI_BASE, DOVE_IRQ_TWSI },
+ { DOVE(88AP510), "mvspi", 0, DOVE_SPI0_BASE, DOVE_IRQ_SPI0 },
+ { DOVE(88AP510), "mvspi", 1, DOVE_SPI1_BASE, DOVE_IRQ_SPI1 },
+ { DOVE(88AP510), "mvcesa", 0, DOVE_CESA_BASE, DOVE_IRQ_SECURITYINT },
+ { DOVE(88AP510), "ehci", 0, DOVE_USB0_BASE, DOVE_IRQ_USB0CNT },
+ { DOVE(88AP510), "ehci", 1, DOVE_USB1_BASE, DOVE_IRQ_USB1CNT },
+ { DOVE(88AP510), "gtidmac", 0, DOVE_XORE_BASE, IRQ_DEFAULT },
+ { DOVE(88AP510), "mvgbec", 0, DOVE_GBE_BASE, IRQ_DEFAULT },
+ { DOVE(88AP510), "mvpex", 0, MVSOC_PEX_BASE, DOVE_IRQ_PEX0_INT },
+ { DOVE(88AP510), "mvpex", 1, DOVE_PEX1_BASE, DOVE_IRQ_PEX1_INT },
+ { DOVE(88AP510), "sdhc", 0, DOVE_SDHC0_BASE, DOVE_IRQ_SD0 },
+ { DOVE(88AP510), "sdhc", 1, DOVE_SDHC1_BASE, DOVE_IRQ_SD1 },
+ { DOVE(88AP510), "mvsata", 0, DOVE_SATAHC_BASE, DOVE_IRQ_SATAINT },
+// { DOVE(88AP510), "mvsocgpp",0, MVSOC_GPP_BASE, IRQ_DEFAULT },
+ { DOVE(88AP510), "mvsocrtc",0, DOVE_RTC_BASE, IRQ_DEFAULT },
+#endif
+
#if defined(ARMADAXP)
{ ARMADAXP(MV78130), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 },
{ ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 },
@@ -1158,6 +1245,9 @@ mvsoc_target(int tag, uint32_t *target,
tag == MARVELL_TAG_SDRAM_CS2 ||
tag == MARVELL_TAG_SDRAM_CS3)
return mvsoc_target_ddr(mvsoc_tags[i].attr, base, size);
+ else if (tag == MARVELL_TAG_AXI_CS0 ||
+ tag == MARVELL_TAG_AXI_CS1)
+ return mvsoc_target_axi(tag, base, size);
else
return mvsoc_target_ddr3(mvsoc_tags[i].attr, base,
size);
@@ -1263,6 +1353,42 @@ mvsoc_target_ddr3(uint32_t attr, uint32_
}
static int
+mvsoc_target_axi(int tag, uint32_t *base, uint32_t *size)
+{
+ uint32_t val;
+ int cs;
+
+ /*
+ * Read MMAP1 Chip Select N the other side of AXI DDR Registers
+ */
+
+ switch (tag) {
+ case MARVELL_TAG_AXI_CS0:
+ cs = 0;
+ break;
+ case MARVELL_TAG_AXI_CS1:
+ cs = 1;
+ break;
+ default:
+ aprint_error("unknwon TAG: 0x%x", tag);
+ return -1;
+ }
+ val = *(volatile uint32_t *)(regbase + MVSOC_AXI_MMAP1(cs));
+ if (val & MVSOC_AXI_MMAP1_VALID) {
+ if (base != NULL)
+ *base = MVSOC_AXI_MMAP1_STARTADDRESS(val);
+ if (size != NULL)
+ *size = MVSOC_AXI_MMAP1_AREALENGTH(val);
+ } else {
+ if (base != NULL)
+ *base = 0;
+ if (size != NULL)
+ *size = 0;
+ }
+ return 0;
+}
+
+static int
mvsoc_target_peripheral(uint32_t target, uint32_t attr, uint32_t *base,
uint32_t *size)
{
Index: src/sys/arch/arm/marvell/mvsoc_space.c
diff -u src/sys/arch/arm/marvell/mvsoc_space.c:1.7 src/sys/arch/arm/marvell/mvsoc_space.c:1.8
--- src/sys/arch/arm/marvell/mvsoc_space.c:1.7 Sat Feb 22 20:33:00 2014
+++ src/sys/arch/arm/marvell/mvsoc_space.c Sat Jan 7 16:19:28 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsoc_space.c,v 1.7 2014/02/22 20:33:00 matt Exp $ */
+/* $NetBSD: mvsoc_space.c,v 1.8 2017/01/07 16:19:28 kiyohara Exp $ */
/*
* Copyright (c) 2007 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mvsoc_space.c,v 1.7 2014/02/22 20:33:00 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mvsoc_space.c,v 1.8 2017/01/07 16:19:28 kiyohara Exp $");
#include "opt_mvsoc.h"
#include "mvpex.h"
@@ -215,6 +215,45 @@ struct bus_space kirkwood_pex1_io_bs_tag
};
#endif
+#if defined(DOVE)
+struct bus_space dove_pex0_mem_bs_tag = {
+ /* cookie */
+ (void *)DOVE_TAG_PEX0_MEM,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS,
+#ifdef __BUS_SPACE_HAS_STREAM_METHODS
+ MVSOC_BUS_SPACE_NORMAL_FUNCS,
+#endif
+};
+struct bus_space dove_pex0_io_bs_tag = {
+ /* cookie */
+ (void *)DOVE_TAG_PEX0_IO,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS,
+#ifdef __BUS_SPACE_HAS_STREAM_METHODS
+ MVSOC_BUS_SPACE_NORMAL_FUNCS,
+#endif
+};
+struct bus_space dove_pex1_mem_bs_tag = {
+ /* cookie */
+ (void *)DOVE_TAG_PEX1_MEM,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS,
+#ifdef __BUS_SPACE_HAS_STREAM_METHODS
+ MVSOC_BUS_SPACE_NORMAL_FUNCS,
+#endif
+};
+struct bus_space dove_pex1_io_bs_tag = {
+ /* cookie */
+ (void *)DOVE_TAG_PEX1_IO,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS,
+#ifdef __BUS_SPACE_HAS_STREAM_METHODS
+ MVSOC_BUS_SPACE_NORMAL_FUNCS,
+#endif
+};
+#endif
+
#if defined(ARMADAXP)
struct bus_space armadaxp_pex00_mem_bs_tag = {
/* cookie */
Index: src/sys/arch/arm/marvell/mvsocreg.h
diff -u src/sys/arch/arm/marvell/mvsocreg.h:1.12 src/sys/arch/arm/marvell/mvsocreg.h:1.13
--- src/sys/arch/arm/marvell/mvsocreg.h:1.12 Wed Jun 3 03:04:21 2015
+++ src/sys/arch/arm/marvell/mvsocreg.h Sat Jan 7 16:19:28 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsocreg.h,v 1.12 2015/06/03 03:04:21 hsuenaga Exp $ */
+/* $NetBSD: mvsocreg.h,v 1.13 2017/01/07 16:19:28 kiyohara Exp $ */
/*
* Copyright (c) 2007, 2008 KIYOHARA Takashi
* All rights reserved.
@@ -35,6 +35,9 @@
#define MVSOC_UNITID_PEX 0x4 /* PCI Express Interface reg */
+#define MVSOC_INTERREGS_SIZE 0x00100000 /* 1 MB */
+
+
/*
* Physical address of integrated peripherals
*/
@@ -193,4 +196,18 @@
*/
#define MVSOC_PEX_BASE (UNITID2PHYS(PEX)) /* 0x40000 */
+
+/*
+ * AXI's DDR Controller Registers
+ * used by Dove only ???
+ */
+
+/* DDR SDRAM Contriller Address Decode Registers */
+#define MVSOC_AXI_NCS 2
+#define MVSOC_AXI_MMAP1(cs) (((cs) << 4) + 0x100)
+#define MVSOC_AXI_MMAP1_STARTADDRESS(v) ((v) & 0xff800000)
+#define MVSOC_AXI_MMAP1_AREALENGTH(v) (0x10000 << (((v) & 0xf0000) >> 16))
+#define MVSOC_AXI_MMAP1_ADDRESSMASK (0x1ff << 7)
+#define MVSOC_AXI_MMAP1_VALID (1 << 0)
+
#endif /* _MVSOCREG_H_ */
Index: src/sys/arch/arm/marvell/mvsocvar.h
diff -u src/sys/arch/arm/marvell/mvsocvar.h:1.10 src/sys/arch/arm/marvell/mvsocvar.h:1.11
--- src/sys/arch/arm/marvell/mvsocvar.h:1.10 Wed Jun 3 04:20:02 2015
+++ src/sys/arch/arm/marvell/mvsocvar.h Sat Jan 7 16:19:28 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsocvar.h,v 1.10 2015/06/03 04:20:02 hsuenaga Exp $ */
+/* $NetBSD: mvsocvar.h,v 1.11 2017/01/07 16:19:28 kiyohara Exp $ */
/*
* Copyright (c) 2007, 2010 KIYOHARA Takashi
* All rights reserved.
@@ -107,6 +107,17 @@ enum mvsoc_tags {
MV78XX0_TAG_PEX13_IO,
MV78XX0_TAG_CRYPT,
+ DOVE_TAG_PEX0_MEM,
+ DOVE_TAG_PEX0_IO,
+ DOVE_TAG_PEX1_MEM,
+ DOVE_TAG_PEX1_IO,
+ DOVE_TAG_CRYPT,
+ DOVE_TAG_SPI0,
+ DOVE_TAG_SPI1,
+ DOVE_TAG_BOOTROM,
+ DOVE_TAG_NAND,
+ DOVE_TAG_PMU,
+
ARMADAXP_TAG_PEX00_MEM,
ARMADAXP_TAG_PEX00_IO,
ARMADAXP_TAG_PEX01_MEM,
@@ -126,21 +137,13 @@ int mvsoc_target(int, uint32_t *, uint32
int mvsoc_target_dump(struct mvsoc_softc *);
int mvsoc_attr_dump(struct mvsoc_softc *, uint32_t, uint32_t);
+extern void (*mvsoc_intr_init)(void);
extern int (*mvsoc_clkgating)(struct marvell_attach_args *);
-void orion_intr_bootstrap(void);
-void orion_getclks(bus_addr_t);
-
-void kirkwood_intr_bootstrap(void);
-void kirkwood_getclks(bus_addr_t);
-int kirkwood_clkgating(struct marvell_attach_args *);
-
-void mv78xx0_intr_bootstrap(void);
-void mv78xx0_getclks(bus_addr_t);
-
-void armadaxp_intr_bootstrap(bus_addr_t);
-void armadaxp_getclks(void);
-void armada370_getclks(void);
-int armadaxp_clkgating(struct marvell_attach_args *);
+void orion_bootstrap(vaddr_t);
+void kirkwood_bootstrap(vaddr_t);
+void mv78xx0_bootstrap(vaddr_t);
+void dove_bootstrap(vaddr_t);
+void armadaxp_bootstrap(vaddr_t, bus_addr_t);
#endif /* _MVSOCVAR_H_ */
Index: src/sys/arch/arm/marvell/orion.c
diff -u src/sys/arch/arm/marvell/orion.c:1.5 src/sys/arch/arm/marvell/orion.c:1.6
--- src/sys/arch/arm/marvell/orion.c:1.5 Tue Jan 28 13:18:42 2014
+++ src/sys/arch/arm/marvell/orion.c Sat Jan 7 16:19:28 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: orion.c,v 1.5 2014/01/28 13:18:42 martin Exp $ */
+/* $NetBSD: orion.c,v 1.6 2017/01/07 16:19:28 kiyohara Exp $ */
/*
* Copyright (c) 2010 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: orion.c,v 1.5 2014/01/28 13:18:42 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: orion.c,v 1.6 2017/01/07 16:19:28 kiyohara Exp $");
#define _INTR_PRIVATE
@@ -56,6 +56,8 @@ static void orion_pic_source_name(struct
static int orion_find_pending_irqs(void);
+static void orion_getclks(vaddr_t);
+
static const char * const sources[64] = {
"Bridge(0)", "Host2CPU DB(1)", "CPU2Host DB(2)", "UART0(3)",
"UART1(4)", "TWSI(5)", "GPIO7_0(6)", "GPIO15_8(7)",
@@ -81,15 +83,14 @@ static struct pic_softc orion_pic = {
/*
- * orion_intr_bootstrap:
+ * orion_bootstrap:
*
- * Initialize the rest of the interrupt subsystem, making it
+ * Initialize the rest of the Orion dependences, making it
* ready to handle interrupts from devices.
*/
void
-orion_intr_bootstrap(void)
+orion_bootstrap(vaddr_t iobase)
{
- extern void (*mvsoc_intr_init)(void);
/* disable all interrupts */
write_mlmbreg(ORION_MLMB_MIRQIMR, 0);
@@ -103,6 +104,8 @@ orion_intr_bootstrap(void)
gpp_npins = 32;
gpp_irqbase = 64; /* Main(32) + Bridge(32) */
#endif
+
+ orion_getclks(iobase);
}
static void
@@ -173,8 +176,8 @@ orion_find_pending_irqs(void)
* Clock functions
*/
-void
-orion_getclks(bus_addr_t iobase)
+static void
+orion_getclks(vaddr_t iobase)
{
static const struct {
int armddrclkval;
Index: src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c
diff -u src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c:1.11 src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c:1.12
--- src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c:1.11 Sun May 3 14:38:10 2015
+++ src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c Sat Jan 7 16:19:29 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp_machdep.c,v 1.11 2015/05/03 14:38:10 hsuenaga Exp $ */
+/* $NetBSD: armadaxp_machdep.c,v 1.12 2017/01/07 16:19:29 kiyohara Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
*******************************************************************************/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp_machdep.c,v 1.11 2015/05/03 14:38:10 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp_machdep.c,v 1.12 2017/01/07 16:19:29 kiyohara Exp $");
#include "opt_machdep.h"
#include "opt_mvsoc.h"
@@ -146,10 +146,6 @@ extern int KERNEL_BASE_phys[];
#define KERNEL_VM_BASE (KERNEL_BASE + 0x40000000)
#define KERNEL_VM_SIZE 0x14000000
-/* Prototypes */
-extern int armadaxp_l2_init(bus_addr_t);
-extern void armadaxp_io_coherency_init(void);
-
void consinit(void);
#ifdef KGDB
static void kgdb_port_init(void);
@@ -198,7 +194,7 @@ static const struct pmap_devmap devmap[]
/* Internal registers */
.pd_va = _A(MARVELL_INTERREGS_VBASE),
.pd_pa = _A(MARVELL_INTERREGS_PBASE),
- .pd_size = _S(MARVELL_INTERREGS_SIZE),
+ .pd_size = _S(MVSOC_INTERREGS_SIZE),
.pd_prot = VM_PROT_READ|VM_PROT_WRITE,
.pd_cache = PTE_NOCACHE
},
@@ -344,37 +340,9 @@ initarm(void *arg)
reset_axp_pcie_win();
/* Get CPU, system and timebase frequencies */
- extern vaddr_t misc_base;
- misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE;
- switch (mvsoc_model()) {
- case MARVELL_ARMADA370_MV6707:
- case MARVELL_ARMADA370_MV6710:
- case MARVELL_ARMADA370_MV6W11:
- armada370_getclks();
- break;
- case MARVELL_ARMADAXP_MV78130:
- case MARVELL_ARMADAXP_MV78160:
- case MARVELL_ARMADAXP_MV78230:
- case MARVELL_ARMADAXP_MV78260:
- case MARVELL_ARMADAXP_MV78460:
- default:
- armadaxp_getclks();
- break;
- }
- mvsoc_clkgating = armadaxp_clkgating;
-
- /* Preconfigure interrupts */
- armadaxp_intr_bootstrap(MARVELL_INTERREGS_PBASE);
-
-#ifdef L2CACHE_ENABLE
- /* Initialize L2 Cache */
- (void)armadaxp_l2_init(MARVELL_INTERREGS_PBASE);
-#endif
-
-#ifdef AURORA_IO_CACHE_COHERENCY
- /* Initialize cache coherency */
- armadaxp_io_coherency_init();
-#endif
+ armadaxp_bootstrap(
+ MARVELL_INTERREGS_VBASE,
+ MARVELL_INTERREGS_PBASE);
#ifdef KGDB
kgdb_port_init();
Index: src/sys/arch/evbarm/marvell/marvell_machdep.c
diff -u src/sys/arch/evbarm/marvell/marvell_machdep.c:1.32 src/sys/arch/evbarm/marvell/marvell_machdep.c:1.33
--- src/sys/arch/evbarm/marvell/marvell_machdep.c:1.32 Wed Jun 3 03:25:51 2015
+++ src/sys/arch/evbarm/marvell/marvell_machdep.c Sat Jan 7 16:19:29 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: marvell_machdep.c,v 1.32 2015/06/03 03:25:51 hsuenaga Exp $ */
+/* $NetBSD: marvell_machdep.c,v 1.33 2017/01/07 16:19:29 kiyohara Exp $ */
/*
* Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi
* All rights reserved.
@@ -25,7 +25,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.32 2015/06/03 03:25:51 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.33 2017/01/07 16:19:29 kiyohara Exp $");
#include "opt_evbarm_boardtype.h"
#include "opt_ddb.h"
@@ -66,6 +66,7 @@ __KERNEL_RCSID(0, "$NetBSD: marvell_mach
#include <arm/marvell/orionreg.h>
#include <arm/marvell/kirkwoodreg.h>
#include <arm/marvell/mv78xx0reg.h>
+#include <arm/marvell/dovereg.h>
#include <arm/marvell/armadaxpreg.h>
#include <arm/marvell/armadaxpvar.h>
#include <arm/marvell/mvsocgppvar.h>
@@ -169,7 +170,7 @@ marvell_fixup_mbus_pex(int memtag, int i
#endif
}
-#if defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0)
+#if defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0) || defined(DOVE)
static void
marvell_system_reset(void)
{
@@ -260,7 +261,7 @@ static struct pmap_devmap marvell_devmap
{
MARVELL_INTERREGS_VBASE,
_A(MARVELL_INTERREGS_PBASE),
- _S(MARVELL_INTERREGS_SIZE),
+ _S(MVSOC_INTERREGS_SIZE),
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
@@ -328,7 +329,7 @@ initarm(void *arg)
case MARVELL_ORION_2_88F5281:
cpu_reset_address = marvell_system_reset;
- orion_intr_bootstrap();
+ orion_bootstrap(MARVELL_INTERREGS_VBASE);
memtag = ORION_TAG_PEX0_MEM;
iotag = ORION_TAG_PEX0_IO;
@@ -338,7 +339,6 @@ initarm(void *arg)
cs = MARVELL_TAG_SDRAM_CS0;
cs_end = MARVELL_TAG_SDRAM_CS3;
- orion_getclks(MARVELL_INTERREGS_VBASE);
marvell_fixup_mbus(memtag, iotag);
break;
#endif /* ORION */
@@ -350,7 +350,7 @@ initarm(void *arg)
case MARVELL_KIRKWOOD_88F6282:
cpu_reset_address = marvell_system_reset;
- kirkwood_intr_bootstrap();
+ kirkwood_bootstrap(MARVELL_INTERREGS_VBASE);
memtag = KIRKWOOD_TAG_PEX_MEM;
iotag = KIRKWOOD_TAG_PEX_IO;
@@ -360,8 +360,6 @@ initarm(void *arg)
cs = MARVELL_TAG_SDRAM_CS0;
cs_end = MARVELL_TAG_SDRAM_CS3;
- kirkwood_getclks(MARVELL_INTERREGS_VBASE);
- mvsoc_clkgating = kirkwood_clkgating;
marvell_fixup_mbus(memtag, iotag);
break;
#endif /* KIRKWOOD */
@@ -371,7 +369,7 @@ initarm(void *arg)
case MARVELL_MV78XX0_MV78200:
cpu_reset_address = marvell_system_reset;
- mv78xx0_intr_bootstrap();
+ mv78xx0_bootstrap(MARVELL_INTERREGS_VBASE);
memtag = MV78XX0_TAG_PEX0_MEM;
iotag = MV78XX0_TAG_PEX0_IO;
@@ -381,52 +379,42 @@ initarm(void *arg)
cs = MARVELL_TAG_SDRAM_CS0;
cs_end = MARVELL_TAG_SDRAM_CS3;
- mv78xx0_getclks(MARVELL_INTERREGS_VBASE);
marvell_fixup_mbus(memtag, iotag);
break;
#endif /* MV78XX0 */
-#ifdef ARMADAXP
- case MARVELL_ARMADAXP_MV78130:
- case MARVELL_ARMADAXP_MV78160:
- case MARVELL_ARMADAXP_MV78230:
- case MARVELL_ARMADAXP_MV78260:
- case MARVELL_ARMADAXP_MV78460:
- cpu_reset_address = armadaxp_system_reset;
-
- armadaxp_intr_bootstrap(MARVELL_INTERREGS_PBASE);
-
- memtag = ARMADAXP_TAG_PEX00_MEM;
- iotag = ARMADAXP_TAG_PEX00_IO;
- nwindow = ARMADAXP_MLMB_NWINDOW;
- nremap = ARMADAXP_MLMB_NREMAP;
+#ifdef DOVE
+ case MARVELL_DOVE_88AP510:
+ cpu_reset_address = marvell_system_reset;
- cs = MARVELL_TAG_DDR3_CS0;
- cs_end = MARVELL_TAG_DDR3_CS3;
+ dove_bootstrap(MARVELL_INTERREGS_VBASE);
- extern vaddr_t misc_base;
- misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE;
- armadaxp_getclks();
- mvsoc_clkgating = armadaxp_clkgating;
- armadaxp_fixup_mbus(memtag, iotag);
+ memtag = DOVE_TAG_PEX0_MEM;
+ iotag = DOVE_TAG_PEX0_IO;
+ nwindow = DOVE_DB_NWINDOW;
+ nremap = DOVE_DB_NREMAP;
-#ifdef L2CACHE_ENABLE
- /* Initialize L2 Cache */
- armadaxp_l2_init(MARVELL_INTERREGS_PBASE);
-#endif
+ cs = MARVELL_TAG_AXI_CS0;
+ cs_end = MARVELL_TAG_AXI_CS1;
-#ifdef AURORA_IO_CACHE_COHERENCY
- /* Initialize cache coherency */
- armadaxp_io_coherency_init();
-#endif
+ marvell_fixup_mbus(memtag, iotag);
break;
+#endif /* DOVE */
+#ifdef ARMADAXP
+ case MARVELL_ARMADAXP_MV78130:
+ case MARVELL_ARMADAXP_MV78160:
+ case MARVELL_ARMADAXP_MV78230:
+ case MARVELL_ARMADAXP_MV78260:
+ case MARVELL_ARMADAXP_MV78460:
case MARVELL_ARMADA370_MV6707:
case MARVELL_ARMADA370_MV6710:
case MARVELL_ARMADA370_MV6W11:
cpu_reset_address = armadaxp_system_reset;
- armadaxp_intr_bootstrap(MARVELL_INTERREGS_PBASE);
+ armadaxp_bootstrap(
+ MARVELL_INTERREGS_VBASE,
+ MARVELL_INTERREGS_PBASE);
memtag = ARMADAXP_TAG_PEX00_MEM;
iotag = ARMADAXP_TAG_PEX00_IO;
@@ -436,21 +424,7 @@ initarm(void *arg)
cs = MARVELL_TAG_DDR3_CS0;
cs_end = MARVELL_TAG_DDR3_CS3;
- extern vaddr_t misc_base;
- misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE;
- armada370_getclks();
- mvsoc_clkgating = armadaxp_clkgating;
armadaxp_fixup_mbus(memtag, iotag);
-
-#ifdef L2CACHE_ENABLE
- /* Initialize L2 Cache */
- (void)armadaxp_l2_init(MARVELL_INTERREGS_PBASE);
-#endif
-
-#ifdef AURORA_IO_CACHE_COHERENCY
- /* Initialize cache coherency */
- armadaxp_io_coherency_init();
-#endif
break;
#endif /* ARMADAXP */
@@ -483,9 +457,9 @@ initarm(void *arg)
paddr_t segment_end;
segment_end = physmem = 0;
for ( ; cs <= cs_end; cs++) {
- uint32_t target, attr, base, size;
+ uint32_t base, size;
- mvsoc_target(cs, &target, &attr, &base, &size);
+ mvsoc_target(cs, NULL, NULL, &base, &size);
if (size == 0)
continue;
@@ -652,6 +626,11 @@ marvell_device_register(device_t dev, vo
kirkwood_pex_io_bs_tag, kirkwood_pex_mem_bs_tag,
kirkwood_pex1_io_bs_tag, kirkwood_pex1_mem_bs_tag;
#endif
+#ifdef DOVE
+ extern struct bus_space
+ dove_pex0_io_bs_tag, dove_pex0_mem_bs_tag,
+ dove_pex1_io_bs_tag, dove_pex1_mem_bs_tag;
+#endif
#ifdef ARMADAXP
extern struct bus_space
armadaxp_pex00_io_bs_tag, armadaxp_pex00_mem_bs_tag,
@@ -719,6 +698,24 @@ marvell_device_register(device_t dev, vo
break;
#endif
+#ifdef DOVE
+ case MARVELL_DOVE_88AP510:
+ if (mva->mva_offset == MVSOC_PEX_BASE) {
+ mvpex_io_bs_tag = &dove_pex0_io_bs_tag;
+ mvpex_mem_bs_tag = &dove_pex0_mem_bs_tag;
+ arm32_mvpex_chipset = &arm32_mvpex0_chipset;
+ iotag = DOVE_TAG_PEX0_IO;
+ memtag = DOVE_TAG_PEX0_MEM;
+ } else {
+ mvpex_io_bs_tag = &dove_pex1_io_bs_tag;
+ mvpex_mem_bs_tag = &dove_pex1_mem_bs_tag;
+ arm32_mvpex_chipset = &arm32_mvpex1_chipset;
+ iotag = DOVE_TAG_PEX1_IO;
+ memtag = DOVE_TAG_PEX1_MEM;
+ }
+ break;
+#endif
+
#ifdef ARMADAXP
case MARVELL_ARMADAXP_MV78130:
case MARVELL_ARMADAXP_MV78160:
Index: src/sys/arch/evbarm/marvell/marvellreg.h
diff -u src/sys/arch/evbarm/marvell/marvellreg.h:1.4 src/sys/arch/evbarm/marvell/marvellreg.h:1.5
--- src/sys/arch/evbarm/marvell/marvellreg.h:1.4 Sat Mar 15 13:56:19 2014
+++ src/sys/arch/evbarm/marvell/marvellreg.h Sat Jan 7 16:19:29 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: marvellreg.h,v 1.4 2014/03/15 13:56:19 kiyohara Exp $ */
+/* $NetBSD: marvellreg.h,v 1.5 2017/01/07 16:19:29 kiyohara Exp $ */
/*
* Copyright (c) 2007 KIYOHARA Takashi
* All rights reserved.
@@ -40,7 +40,6 @@
#else
#define MARVELL_INTERREGS_PBASE 0xf1000000
#endif
-#define MARVELL_INTERREGS_SIZE 0x00100000
#define MARVELL_PEXIO_PBASE 0xf2000000
#define MARVELL_PEXIO_SIZE 0x00100000
Added files:
Index: src/sys/arch/arm/marvell/dove.c
diff -u /dev/null src/sys/arch/arm/marvell/dove.c:1.1
--- /dev/null Sat Jan 7 16:19:29 2017
+++ src/sys/arch/arm/marvell/dove.c Sat Jan 7 16:19:28 2017
@@ -0,0 +1,562 @@
+/* $NetBSD: dove.c,v 1.1 2017/01/07 16:19:28 kiyohara Exp $ */
+/*
+ * Copyright (c) 2016 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: dove.c,v 1.1 2017/01/07 16:19:28 kiyohara Exp $");
+
+#define _INTR_PRIVATE
+
+#include "mvsocgpp.h"
+#include "mvsocpmu.h"
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/errno.h>
+
+#include <machine/intr.h>
+
+#include <arm/cpufunc.h>
+#include <arm/pic/picvar.h>
+#include <arm/pic/picvar.h>
+
+#include <arm/marvell/mvsocreg.h>
+#include <arm/marvell/mvsocvar.h>
+#include <arm/marvell/mvsocpmuvar.h>
+#include <arm/marvell/dovereg.h>
+
+#include <dev/marvell/marvellreg.h>
+
+
+#define read_dbreg read_mlmbreg
+#define write_dbreg write_mlmbreg
+#if NMVSOCPMU > 0
+#define READ_PMUREG(sc, o) \
+ bus_space_read_4((sc)->sc_iot, (sc)->sc_pmch, (o))
+#define WRITE_PMUREG(sc, o, v) \
+ bus_space_write_4((sc)->sc_iot, (sc)->sc_pmch, (o), (v))
+#else
+vaddr_t pmu_base = -1;
+#define READ_PMUREG(sc, o) (*(volatile uint32_t *)(pmu_base + (o)))
+#endif
+
+static void dove_intr_init(void);
+
+static void dove_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
+static void dove_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
+static void dove_pic_establish_irq(struct pic_softc *, struct intrsource *);
+static void dove_pic_source_name(struct pic_softc *, int, char *, size_t);
+
+static int dove_find_pending_irqs(void);
+
+static void dove_getclks(bus_addr_t);
+static int dove_clkgating(struct marvell_attach_args *);
+
+#if NMVSOCPMU > 0
+struct dove_pmu_softc {
+ struct mvsocpmu_softc sc_mvsocpmu_sc;
+
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_pmch; /* Power Management Core handler */
+ bus_space_handle_t sc_pmh; /* Power Management handler */
+
+ int sc_xpratio;
+ int sc_dpratio;
+};
+static int dove_pmu_match(device_t, struct cfdata *, void *);
+static void dove_pmu_attach(device_t, device_t, void *);
+static int dove_pmu_intr(void *);
+static int dove_tm_val2uc(int);
+static int dove_tm_uc2val(int);
+static int dove_dfs_slow(struct dove_pmu_softc *, bool);
+
+CFATTACH_DECL_NEW(mvsocpmu, sizeof(struct dove_pmu_softc),
+ dove_pmu_match, dove_pmu_attach, NULL, NULL);
+#endif
+
+
+static const char * const sources[64] = {
+ "Bridge(0)", "Host2CPUDoorbell(1)","CPU2HostDoorbell(2)","NF(3)",
+ "PDMA(4)", "SPI1(5)", "SPI0(6)", "UART0(7)",
+ "UART1(8)", "UART2(9)", "UART3(10)", "TWSI(11)",
+ "GPIO7_0(12)", "GPIO15_8(13)", "GPIO23_16(14)", "PEX0_Err(15)",
+ "PEX0_INT(16)", "PEX1_Err(17)", "PEX1_INT(18)", "Audio0_INT(19)",
+ "Audio0_Err(20)", "Audio1_INT(21)", "Audio1_Err(22)", "USBBr(23)",
+ "USB0Cnt(24)", "USB1Cnt(25)", "GbERx(26)", "GbETx(27)",
+ "GbEMisc(28)", "GbESum(29)", "GbEErr(30)", "SecurityInt(31)",
+
+ "AC97(32)", "PMU(33)", "CAM(34)", "SD0(35)",
+ "SD1(36)", "SD0_wakeup_Int(37)","SD1_wakeup_Int(38)","XOR0_DMA0(39)",
+ "XOR0_DMA1(40)", "XOR0Err(41)", "XOR1_DMA0(42)", "XOR1_DMA1(43)",
+ "XOR1Err(44)", "IRE_DCON(45)", "LCD1(46)", "LCD0(47)",
+ "GPU(48)", "Reserved(49)", "Reserved_18(50)", "Vmeta(51)",
+ "Reserved_20(52)", "Reserved_21(53)", "SSPTimer(54)", "SSPInt(55)",
+ "MemoryErr(56)", "DwnstrmExclTrn(57)","UpstrmAddrErr(58)","SecurityErr(59)",
+ "GPIO_31_24(60)", "HighGPIO(61)", "SATAInt(62)", "Reserved_31(63)"
+};
+
+static struct pic_ops dove_picops = {
+ .pic_unblock_irqs = dove_pic_unblock_irqs,
+ .pic_block_irqs = dove_pic_block_irqs,
+ .pic_establish_irq = dove_pic_establish_irq,
+ .pic_source_name = dove_pic_source_name,
+};
+static struct pic_softc dove_pic = {
+ .pic_ops = &dove_picops,
+ .pic_maxsources = 64,
+ .pic_name = "dove",
+};
+
+static struct {
+ bus_size_t offset;
+ uint32_t bits;
+} clkgatings[]= {
+ { DOVE_USB0_BASE, (1 << 0) },
+ { DOVE_USB1_BASE, (1 << 1) },
+ { DOVE_GBE_BASE, (1 << 2) | (1 << 30) },
+ { DOVE_SATAHC_BASE, (1 << 3) },
+ { MVSOC_PEX_BASE, (1 << 4) },
+ { DOVE_PEX1_BASE, (1 << 5) },
+ { DOVE_SDHC0_BASE, (1 << 8) },
+ { DOVE_SDHC1_BASE, (1 << 9) },
+ { DOVE_NAND_BASE, (1 << 10) },
+ { DOVE_CAMERA_BASE, (1 << 11) },
+ { DOVE_AUDIO0_BASE, (1 << 12) },
+ { DOVE_AUDIO1_BASE, (1 << 13) },
+ { DOVE_CESA_BASE, (1 << 15) },
+#if 0
+ { PDMA, (1 << 22) }, /* PdmaEnClock */
+#endif
+ { DOVE_XORE_BASE, (1 << 23) | (1 << 24) },
+};
+
+
+/*
+ * dove_bootstrap:
+ *
+ * Initialize the rest of the Dove dependencies, making it
+ * ready to handle interrupts from devices.
+ * And clks, PMU.
+ */
+void
+dove_bootstrap(bus_addr_t iobase)
+{
+
+ /* disable all interrupts */
+ write_dbreg(DOVE_DB_MIRQIMR, 0);
+ write_dbreg(DOVE_DB_SMIRQIMR, 0);
+
+ /* disable all bridge interrupts */
+ write_mlmbreg(MVSOC_MLMB_MLMBIMR, 0);
+
+ mvsoc_intr_init = dove_intr_init;
+
+#if NMVSOCGPP > 0
+ /*
+ * 64 General Purpose Port I/O (GPIO [63:0]) and
+ * an additional eight General Purpose Outputs (GPO [71:64]).
+ */
+ gpp_npins = 72;
+ gpp_irqbase = 96; /* Main(32) + Second Main(32) + Bridge(32) */
+#endif
+
+ dove_getclks(iobase);
+
+ mvsoc_clkgating = dove_clkgating;
+#if NMVSOCPMU == 0
+ pmu_base = iobase + DOVE_PMU_BASE;
+#endif
+}
+
+static void
+dove_intr_init(void)
+{
+ extern struct pic_softc mvsoc_bridge_pic;
+ void *ih __diagused;
+
+ pic_add(&dove_pic, 0);
+
+ pic_add(&mvsoc_bridge_pic, 64);
+ ih = intr_establish(DOVE_IRQ_BRIDGE, IPL_HIGH, IST_LEVEL_HIGH,
+ pic_handle_intr, &mvsoc_bridge_pic);
+ KASSERT(ih != NULL);
+
+ find_pending_irqs = dove_find_pending_irqs;
+}
+
+/* ARGSUSED */
+static void
+dove_pic_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
+{
+ const size_t reg = DOVE_DB_MIRQIMR
+ + irqbase * (DOVE_DB_SMIRQIMR - DOVE_DB_MIRQIMR) / 32;
+
+ KASSERT(irqbase < 64);
+ write_dbreg(reg, read_dbreg(reg) | irq_mask);
+}
+
+/* ARGSUSED */
+static void
+dove_pic_block_irqs(struct pic_softc *pic, size_t irqbase,
+ uint32_t irq_mask)
+{
+ const size_t reg = DOVE_DB_MIRQIMR
+ + irqbase * (DOVE_DB_SMIRQIMR - DOVE_DB_MIRQIMR) / 32;
+
+ KASSERT(irqbase < 64);
+ write_dbreg(reg, read_dbreg(reg) & ~irq_mask);
+}
+
+/* ARGSUSED */
+static void
+dove_pic_establish_irq(struct pic_softc *pic, struct intrsource *is)
+{
+ /* Nothing */
+}
+
+static void
+dove_pic_source_name(struct pic_softc *pic, int irq, char *buf, size_t len)
+{
+
+ strlcpy(buf, sources[pic->pic_irqbase + irq], len);
+}
+
+/*
+ * Called with interrupts disabled
+ */
+static int
+dove_find_pending_irqs(void)
+{
+ int ipl = 0;
+
+ uint32_t cause = read_dbreg(DOVE_DB_MICR);
+ uint32_t pending = read_dbreg(DOVE_DB_MIRQIMR);
+ pending &= cause;
+ if (pending)
+ ipl |= pic_mark_pending_sources(&dove_pic, 0, pending);
+
+ uint32_t cause2 = read_dbreg(DOVE_DB_SMICR);
+ uint32_t pending2 = read_dbreg(DOVE_DB_SMIRQIMR);
+ pending2 &= cause2;
+ if (pending2)
+ ipl |= pic_mark_pending_sources(&dove_pic, 32, pending2);
+
+ return ipl;
+}
+
+/*
+ * Clock functions
+ */
+
+static void
+dove_getclks(bus_addr_t iobase)
+{
+ uint32_t val;
+
+#define MHz * 1000 * 1000
+
+ val = *(volatile uint32_t *)(iobase + DOVE_MISC_BASE +
+ DOVE_MISC_SAMPLE_AT_RESET0);
+
+ switch (val & 0x01800000) {
+ case 0x00000000: mvTclk = 166 MHz; break;
+ case 0x00800000: mvTclk = 125 MHz; break;
+ default:
+ panic("unknown mvTclk\n");
+ }
+
+ switch (val & 0x000001e0) {
+ case 0x000000a0: mvPclk = 1000 MHz; break;
+ case 0x000000c0: mvPclk = 933 MHz; break;
+ case 0x000000e0: mvPclk = 933 MHz; break;
+ case 0x00000100: mvPclk = 800 MHz; break;
+ case 0x00000120: mvPclk = 800 MHz; break;
+ case 0x00000140: mvPclk = 800 MHz; break;
+ case 0x00000160: mvPclk = 1067 MHz; break;
+ case 0x00000180: mvPclk = 667 MHz; break;
+ case 0x000001a0: mvPclk = 533 MHz; break;
+ case 0x000001c0: mvPclk = 400 MHz; break;
+ case 0x000001e0: mvPclk = 333 MHz; break;
+ default:
+ panic("unknown mvPclk\n");
+ }
+
+ switch (val & 0x0000f000) {
+ case 0x00000000: mvSysclk = mvPclk / 1; break;
+ case 0x00002000: mvSysclk = mvPclk / 2; break;
+ case 0x00004000: mvSysclk = mvPclk / 3; break;
+ case 0x00006000: mvSysclk = mvPclk / 4; break;
+ case 0x00008000: mvSysclk = mvPclk / 5; break;
+ case 0x0000a000: mvSysclk = mvPclk / 6; break;
+ case 0x0000c000: mvSysclk = mvPclk / 7; break;
+ case 0x0000e000: mvSysclk = mvPclk / 8; break;
+ case 0x0000f000: mvSysclk = mvPclk / 10; break;
+ }
+
+#undef MHz
+
+}
+
+static int
+dove_clkgating(struct marvell_attach_args *mva)
+{
+ uint32_t val;
+ int i;
+
+#if NMVSOCPMU > 0
+ struct dove_pmu_softc *pmu =
+ device_private(device_find_by_xname("mvsocpmu0"));
+
+ if (pmu == NULL)
+ return 0;
+#else
+ KASSERT(pmu_base != -1);
+#endif
+
+ if (strcmp(mva->mva_name, "mvsocpmu") == 0)
+ return 0;
+
+ for (i = 0; i < __arraycount(clkgatings); i++) {
+ if (clkgatings[i].offset == mva->mva_offset) {
+ val = READ_PMUREG(pmu, DOVE_PMU_CGCR);
+ if ((val & clkgatings[i].bits) == clkgatings[i].bits)
+ /* Clock enabled */
+ return 0;
+ return 1;
+ }
+ }
+ /* Clock Gating not support */
+ return 0;
+}
+
+#if NMVSOCPMU > 0
+static int
+dove_pmu_match(device_t parent, struct cfdata *match, void *aux)
+{
+ struct marvell_attach_args *mva = aux;
+
+ if (mvsocpmu_match(parent, match, aux) == 0)
+ return 0;
+
+ if (mva->mva_offset == MVA_OFFSET_DEFAULT ||
+ mva->mva_irq == MVA_IRQ_DEFAULT)
+ return 0;
+
+ mva->mva_size = DOVE_PMU_SIZE;
+ return 1;
+}
+
+static void
+dove_pmu_attach(device_t parent, device_t self, void *aux)
+{
+ struct dove_pmu_softc *sc = device_private(self);
+ struct marvell_attach_args *mva = aux;
+ uint32_t tdc0, cpucdc0;
+
+ sc->sc_iot = mva->mva_iot;
+ if (bus_space_subregion(sc->sc_iot, mva->mva_ioh,
+ mva->mva_offset, mva->mva_size, &sc->sc_pmch))
+ panic("%s: Cannot map core registers", device_xname(self));
+ if (bus_space_subregion(sc->sc_iot, mva->mva_ioh,
+ mva->mva_offset + (DOVE_PMU_BASE2 - DOVE_PMU_BASE),
+ DOVE_PMU_SIZE, &sc->sc_pmh))
+ panic("%s: Cannot map registers", device_xname(self));
+ if (bus_space_subregion(sc->sc_iot, mva->mva_ioh,
+ mva->mva_offset + (DOVE_PMU_SRAM_BASE - DOVE_PMU_BASE),
+ DOVE_PMU_SRAM_SIZE, &sc->sc_pmh))
+ panic("%s: Cannot map SRAM", device_xname(self));
+
+ tdc0 = READ_PMUREG(sc, DOVE_PMU_TDC0R);
+ tdc0 &= ~(DOVE_PMU_TDC0R_THERMAVGNUM_MASK |
+ DOVE_PMU_TDC0R_THERMREFCALCOUNT_MASK |
+ DOVE_PMU_TDC0R_THERMSELVCAL_MASK);
+ tdc0 |= (DOVE_PMU_TDC0R_THERMAVGNUM_2 |
+ DOVE_PMU_TDC0R_THERMREFCALCOUNT(0xf1) |
+ DOVE_PMU_TDC0R_THERMSELVCAL(2));
+ WRITE_PMUREG(sc, DOVE_PMU_TDC0R, tdc0);
+ WRITE_PMUREG(sc, DOVE_PMU_TDC0R,
+ READ_PMUREG(sc, DOVE_PMU_TDC0R) | DOVE_PMU_TDC0R_THERMSOFTRESET);
+ delay(1);
+ WRITE_PMUREG(sc, DOVE_PMU_TDC0R,
+ READ_PMUREG(sc, DOVE_PMU_TDC0R) & ~DOVE_PMU_TDC0R_THERMSOFTRESET);
+ cpucdc0 = READ_PMUREG(sc, DOVE_PMU_CPUCDC0R);
+ sc->sc_xpratio = DOVE_PMU_CPUCDC0R_XPRATIO(cpucdc0);
+ sc->sc_dpratio = DOVE_PMU_CPUCDC0R_DPRATIO(cpucdc0);
+
+ sc->sc_mvsocpmu_sc.sc_iot = mva->mva_iot;
+
+ if (bus_space_subregion(sc->sc_iot, sc->sc_pmch,
+ DOVE_PMU_TM_BASE, MVSOC_PMU_TM_SIZE, &sc->sc_mvsocpmu_sc.sc_tmh))
+ panic("%s: Cannot map thermal managaer registers",
+ device_xname(self));
+ sc->sc_mvsocpmu_sc.sc_uc2val = dove_tm_uc2val;
+ sc->sc_mvsocpmu_sc.sc_val2uc = dove_tm_val2uc;
+
+ mvsocpmu_attach(parent, self, aux);
+
+ WRITE_PMUREG(sc, DOVE_PMU_PMUICR, 0);
+ WRITE_PMUREG(sc, DOVE_PMU_PMUIMR, DOVE_PMU_PMUI_THERMOVERHEAT);
+
+ marvell_intr_establish(mva->mva_irq, IPL_HIGH, dove_pmu_intr, sc);
+}
+
+static int
+dove_pmu_intr(void *arg)
+{
+ struct dove_pmu_softc *sc = arg;
+ uint32_t cause, mask;
+
+ mask = READ_PMUREG(sc, DOVE_PMU_PMUIMR);
+ cause = READ_PMUREG(sc, DOVE_PMU_PMUICR);
+printf("dove pmu intr: cause 0x%x, mask 0x%x\n", cause, mask);
+ WRITE_PMUREG(sc, DOVE_PMU_PMUICR, 0);
+ cause &= mask;
+
+ if (cause & DOVE_PMU_PMUI_BATTFAULT) {
+printf(" Battery Falut\n");
+ }
+ if (cause & DOVE_PMU_PMUI_RTCALARM) {
+printf(" RTC Alarm\n");
+ }
+ if (cause & DOVE_PMU_PMUI_THERMOVERHEAT) {
+ mask |= DOVE_PMU_PMUI_THERMCOOLING;
+ if (dove_dfs_slow(sc, true) == 0)
+ mask &= ~DOVE_PMU_PMUI_THERMOVERHEAT;
+ WRITE_PMUREG(sc, DOVE_PMU_PMUIMR, mask);
+ }
+ if (cause & DOVE_PMU_PMUI_THERMCOOLING) {
+ mask |= DOVE_PMU_PMUI_THERMOVERHEAT;
+ if (dove_dfs_slow(sc, false) == 0)
+ mask &= ~DOVE_PMU_PMUI_THERMCOOLING;
+ WRITE_PMUREG(sc, DOVE_PMU_PMUIMR, mask);
+ }
+ if (cause & DOVE_PMU_PMUI_DVSDONE) {
+printf(" DVS Done\n");
+ }
+ if (cause & DOVE_PMU_PMUI_DFSDONE) {
+printf(" DFS Done\n");
+ }
+
+ return 0;
+}
+
+static int
+dove_tm_uc2val(int v)
+{
+
+ return (2281638 - v / 1000 * 10) / 7298;
+}
+
+static int
+dove_tm_val2uc(int v)
+{
+
+ return (2281638 - 7298 * v) / 10 * 1000;
+}
+
+static int
+dove_dfs_slow(struct dove_pmu_softc *sc, bool slow)
+{
+ uint32_t control, status, psw, pmucr;
+ int rv;
+uint32_t cause0, cause1, cause2;
+
+ status = READ_PMUREG(sc, DOVE_PMU_CPUSDFSSR);
+ status &= DOVE_PMU_CPUSDFSSR_CPUSLOWMODESTTS_MASK;
+ if ((slow && status == DOVE_PMU_CPUSDFSSR_CPUSLOWMODESTTS_SLOW) ||
+ (!slow && status == DOVE_PMU_CPUSDFSSR_CPUSLOWMODESTTS_TURBO))
+ return 0;
+
+cause0 = READ_PMUREG(sc, DOVE_PMU_PMUICR);
+ /*
+ * 1. Disable the CPU FIQ and IRQ interrupts.
+ */
+ psw = disable_interrupts(I32_bit | F32_bit);
+
+ /*
+ * 2. Program the new CPU Speed mode in the CPU Subsystem DFS Control
+ * Register.
+ */
+ control = READ_PMUREG(sc, DOVE_PMU_CPUSDFSCR);
+ if (slow) {
+ control |= DOVE_PMU_CPUSDFSCR_CPUSLOWEN;
+ control |= DOVE_PMU_CPUSDFSCR_CPUL2CR(sc->sc_dpratio);
+ } else {
+ control &= ~DOVE_PMU_CPUSDFSCR_CPUSLOWEN;
+ control |= DOVE_PMU_CPUSDFSCR_CPUL2CR(sc->sc_xpratio);
+ }
+ WRITE_PMUREG(sc, DOVE_PMU_CPUSDFSCR, control);
+
+ /*
+ * 3. Enable the <DFSDone> field in the PMU Interrupts Mask Register
+ * to wake up the CPU when the DFS procedure has been completed.
+ */
+ WRITE_PMUREG(sc, DOVE_PMU_PMUIMR,
+ READ_PMUREG(sc, DOVE_PMU_PMUIMR) | DOVE_PMU_PMUI_DFSDONE);
+
+ /*
+ * 4. Set the <MaskFIQ> and <MaskIRQ> field in the PMU Control Register.
+ * The PMU masks the main interrupt pins of the Interrupt Controller
+ * (FIQ and IRQ) from, so that they cannot be asserted to the CPU
+ * core.
+ */
+ pmucr = bus_space_read_4(sc->sc_iot, sc->sc_pmh, DOVE_PMU_PMUCR);
+cause1 = READ_PMUREG(sc, DOVE_PMU_PMUICR);
+ bus_space_write_4(sc->sc_iot, sc->sc_pmh, DOVE_PMU_PMUCR,
+ pmucr | DOVE_PMU_PMUCR_MASKFIQ | DOVE_PMU_PMUCR_MASKIRQ);
+
+ /*
+ * 5. Set the <DFSEn> field in the CPU Subsystem DFS Control Register.
+ */
+ WRITE_PMUREG(sc, DOVE_PMU_CPUSDFSCR,
+ READ_PMUREG(sc, DOVE_PMU_CPUSDFSCR) | DOVE_PMU_CPUSDFSCR_DFSEN);
+
+ /*
+ * 6. Use the WFI instruction (Wait for Interrupt), to place the CPU
+ * in Sleep mode.
+ */
+cause2 = READ_PMUREG(sc, DOVE_PMU_PMUICR);
+ __asm("wfi");
+
+ status = READ_PMUREG(sc, DOVE_PMU_CPUSDFSSR);
+ status &= DOVE_PMU_CPUSDFSSR_CPUSLOWMODESTTS_MASK;
+ if ((slow && status == DOVE_PMU_CPUSDFSSR_CPUSLOWMODESTTS_SLOW) ||
+ (!slow && status == DOVE_PMU_CPUSDFSSR_CPUSLOWMODESTTS_TURBO)) {
+ rv = 0;
+ printf("DFS changed to %s\n", slow ? "slow" : "turbo");
+ } else {
+ rv = 1;
+ printf("DFS failed to %s\n", slow ? "slow" : "turbo");
+ }
+
+ bus_space_write_4(sc->sc_iot, sc->sc_pmh, DOVE_PMU_PMUCR, pmucr);
+ restore_interrupts(psw);
+printf("causes: 0x%x -> 0x%x -> 0x%x\n", cause0, cause1, cause2);
+
+ return rv;
+}
+#endif
Index: src/sys/arch/arm/marvell/dovereg.h
diff -u /dev/null src/sys/arch/arm/marvell/dovereg.h:1.1
--- /dev/null Sat Jan 7 16:19:29 2017
+++ src/sys/arch/arm/marvell/dovereg.h Sat Jan 7 16:19:28 2017
@@ -0,0 +1,289 @@
+/* $NetBSD: dovereg.h,v 1.1 2017/01/07 16:19:28 kiyohara Exp $ */
+/*
+ * Copyright (c) 2016 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DOVEREG_H_
+#define _DOVEREG_H_
+
+#include <arm/marvell/mvsocreg.h>
+
+#define DOVE_UNITID_DDR MVSOC_UNITID_DDR
+#define DOVE_UNITID_DEVBUS MVSOC_UNITID_DEVBUS
+#define DOVE_UNITID_DB 0x2 /* Downstream Bridge reg */
+#define DOVE_UNITID_SA 0x3 /* Security Accelelerator reg */
+#define DOVE_UNITID_PEX MVSOC_UNITID_PEX
+#define DOVE_UNITID_USB 0x5
+#define DOVE_UNITID_XOR 0x6
+#define DOVE_UNITID_GBE 0x7
+#define DOVE_UNITID_PEX1 0x8
+#define DOVE_UNITID_SDIO 0x9
+#define DOVE_UNITID_SATA 0xa
+#define DOVE_UNITID_I2S 0xb
+#define DOVE_UNITID_NAND 0xc
+#define DOVE_UNITID_PMU 0xd
+#define DOVE_UNITID_AC97 0xe
+
+#define DOVE_ATTR_PEX_MEM 0xe8
+#define DOVE_ATTR_PEX_IO 0xe0
+#define DOVE_ATTR_SA 0x00
+#define DOVE_ATTR_SPI0 0xfe
+#define DOVE_ATTR_SPI1 0xfb
+#define DOVE_ATTR_BOOTROM 0xfd
+#define DOVE_ATTR_NAND 0x00
+#define DOVE_ATTR_PMU 0x00
+
+#define DOVE_IRQ_BRIDGE 0 /* Downstream Bridge intr */
+#define DOVE_IRQ_H2CPUDB 1 /* Doorbell Interrupt */
+#define DOVE_IRQ_CPU2HDB 2 /* Doorbell Interrupt */
+#define DOVE_IRQ_NF 3 /* NandFlash Interrupt */
+#define DOVE_IRQ_PDMA 4 /* Peripheral DMA Interrupt */
+#define DOVE_IRQ_SPI1 5 /* SPI1 Ready Interrupt */
+#define DOVE_IRQ_SPI0 6 /* SPI9 Ready Interrupt */
+#define DOVE_IRQ_UART0 7 /* UART0 Interrupt */
+#define DOVE_IRQ_UART1 8 /* UART1 Interrupt */
+#define DOVE_IRQ_UART2 9 /* UART2 Interrupt */
+#define DOVE_IRQ_UART3 10 /* UART3 Interrupt */
+#define DOVE_IRQ_TWSI 11 /* TWSI Interrupt */
+#define DOVE_IRQ_GPIO7_0 12 /* GPIO[7:0] Interrupt */
+#define DOVE_IRQ_GPIO15_8 13 /* GPIO[15:8] Interrupt */
+#define DOVE_IRQ_GPIO23_16 14 /* GPIO[23:16] Interrupt */
+#define DOVE_IRQ_PEX0_ERR 15 /* PCI Express0 Error */
+#define DOVE_IRQ_PEX0_INT 16 /*PCI Express0 INT [A-D] mesg*/
+#define DOVE_IRQ_PEX1_ERR 17 /* PCI Express1 Error */
+#define DOVE_IRQ_PEX1_INT 18 /*PCI Express1 INT [A-D] mesg*/
+#define DOVE_IRQ_AUDIO0_INT 19 /* Audio0 Interrupt */
+#define DOVE_IRQ_AUDIO0_ERR 20 /* Audio0 Error */
+#define DOVE_IRQ_AUDIO1_INT 21 /* Audio1 Interrupt */
+#define DOVE_IRQ_AUDIO1_ERR 22 /* Audio1 Error */
+#define DOVE_IRQ_USBBR 23 /* USB Bridge Error */
+#define DOVE_IRQ_USB0CNT 24 /* USB0 Controller Interrupt */
+#define DOVE_IRQ_USB1CNT 25 /* USB1 Controller Interrupt */
+#define DOVE_IRQ_GBERX 26 /* GbE Receive Interrupt */
+#define DOVE_IRQ_GBETX 27 /* GbE Transmit Interrupt */
+#define DOVE_IRQ_GBEMISC 28 /* GbE Miscellaneous intr */
+#define DOVE_IRQ_GBESUM 29 /* GbE Summary */
+#define DOVE_IRQ_GBEERR 30 /* GbE Error */
+#define DOVE_IRQ_SECURITYINT 31 /* Security Interrupt */
+#define DOVE_IRQ_AC97 32 /* AC97 Interrupt */
+#define DOVE_IRQ_PMU 33 /* Power Management Unit intr */
+#define DOVE_IRQ_CAM 34 /* Cafe Camera Interrupt */
+#define DOVE_IRQ_SD0 35 /* SD0 IRQ Interrupt */
+#define DOVE_IRQ_SD1 36 /* SD1 IRQ Interrupt */
+#define DOVE_IRQ_XOR0_DMA0 39 /* XOR Unit DMA0 Completion */
+#define DOVE_IRQ_XOR0_DMA1 40 /* XOR Unit DMA1 Completion */
+#define DOVE_IRQ_XOR0ERR 41 /* XOR Unit Error Interrupt */
+#define DOVE_IRQ_XOR1_DMA0 42 /* XOR Unit DMA0 Completion */
+#define DOVE_IRQ_XOR1_DMA1 43 /* XOR Unit DMA1 Completion */
+#define DOVE_IRQ_XOR1ERR 44 /* XOR Unit Error Interrupt */
+#define DOVE_IRQ_IRE_DCON 45 /* IRE OR DCON Interrupt */
+#define DOVE_IRQ_LCD1 46 /* LCD1 Interrupt */
+#define DOVE_IRQ_LCD0 47 /* LCD0 Interrupt */
+#define DOVE_IRQ_GPU 48 /* GPU Interrupt */
+#define DOVE_IRQ_VMETA 51 /*Video dec Unit Semaphore intr*/
+#define DOVE_IRQ_SSPTIMER 54 /* SSP Timer Interrupt */
+#define DOVE_IRQ_SSPINT 55 /* SSP Interrupt */
+#define DOVE_IRQ_MEMORYERR 56 /*mem Controller or L2 ECC err*/
+#define DOVE_IRQ_DWNSTRMEXCLTM 57
+#define DOVE_IRQ_UPSTRMADDERR 58
+#define DOVE_IRQ_SECURITYERR 59 /* Security Error */
+#define DOVE_IRQ_GPIO_31_24 60 /* Interrupt from GPIO[31:24] */
+#define DOVE_IRQ_HIGHGPIO 61 /* intr from High GPIO[31:0] */
+#define DOVE_IRQ_SATAINT 62 /* SATA Interrupt */
+
+
+/*
+ * Physical address of integrated peripherals
+ */
+
+#define DOVE_UNITID2PHYS(uid) ((DOVE_UNITID_ ## uid) << 16)
+
+/*
+ * SPI Registers
+ */
+#define DOVE_SPI0_BASE (MVSOC_DEVBUS_BASE + 0x0600) /* 0x10600 */
+#define DOVE_SPI1_BASE (MVSOC_DEVBUS_BASE + 0x4600) /* 0x14600 */
+
+/*
+ * UART Interface Registers
+ */
+ /* NS16550 compatible */
+#define DOVE_COM2_BASE (MVSOC_DEVBUS_BASE + 0x2200)
+#define DOVE_COM3_BASE (MVSOC_DEVBUS_BASE + 0x2300)
+
+/*
+ * Downstream Bridge Registers
+ */
+#define DOVE_DB_BASE (DOVE_UNITID2PHYS(DB))
+
+/* CPU Address Map Registers */
+#define DOVE_DB_NWINDOW 8
+#define DOVE_DB_NREMAP 4
+
+/* Main Interrupt Controller Registers */
+#define DOVE_DB_MICR 0x200 /* Main Interrupt Cause reg */
+#define DOVE_DB_MIRQIMR 0x204 /* Main IRQ Interrupt Mask */
+#define DOVE_DB_MFIQIMR 0x208 /* Main FIQ Interrupt Mask */
+#define DOVE_DB_EIMR 0x20c /* Endpoint Interrupt Mask */
+#define DOVE_DB_SMICR 0x210 /* Second Main Intr Cause reg */
+#define DOVE_DB_SMIRQIMR 0x214 /* Second Main IRQ intr Mask */
+#define DOVE_DB_SMFIQIMR 0x218 /* Second Main FIQ intr Mask */
+#define DOVE_DB_SEIMR 0x21c /* Second Endpoint intr Mask */
+#define DOVE_DB_PCIEIMR 0x220 /* PCIe0/PCIe1 intr Mask reg */
+
+
+/*
+ * Cryptographic Engine and Security Accelerator (CESA) Registers
+ */ /* 0x3d000 */
+#define DOVE_CESA_BASE (DOVE_UNITID2PHYS(SA) + 0xd000)
+
+/*
+ * USB 2.0 Interface Registers
+ */
+#define DOVE_USB0_BASE (DOVE_UNITID2PHYS(USB)) /* 0x50000 */
+#define DOVE_USB1_BASE (DOVE_UNITID2PHYS(USB) + 0x1000)
+
+/*
+ * XOR DMA Engine Registers
+ */
+#define DOVE_XORE_BASE (DOVE_UNITID2PHYS(XOR)) /* 0x60000 */
+
+/*
+ * Gigabit Ethernet Controller (GbE) Registers
+ */
+#define DOVE_GBE_BASE (DOVE_UNITID2PHYS(GBE)) /* 0x70000 */
+
+/*
+ * PCI Express (PCIe) Registers
+ */
+#define DOVE_PEX1_BASE (DOVE_UNITID2PHYS(PEX1)) /* 0x80000 */
+
+/*
+ * Camera and SDIO Registers
+ */
+#define DOVE_SDHC_SIZE 0x2000
+#define DOVE_SDHC1_BASE (DOVE_UNITID2PHYS(SDIO)) /* 0x90000 */
+#define DOVE_SDHC0_BASE (DOVE_SDHC1_BASE + DOVE_SDHC_SIZE)
+#define DOVE_CAMERA_BASE (DOVE_SDHC0_BASE + DOVE_SDHC_SIZE)
+
+/*
+ * Serial-ATA Host Controller Registers
+ */
+#define DOVE_SATAHC_BASE (DOVE_UNITID2PHYS(SATA)) /* 0xa0000 */
+
+/*
+ * Audio (I2S/S/PDIF) Interface Registers
+ */
+#define DOVE_AUDIO0_BASE (DOVE_UNITID2PHYS(I2S)) /* 0xb0000 */
+#define DOVE_AUDIO1_BASE (DOVE_UNITID2PHYS(I2S) + 0x4000)
+
+/*
+ * NAND Flash Registers
+ */
+#define DOVE_NAND_BASE (DOVE_UNITID2PHYS(NAND)) /* 0xc0000 */
+
+/*
+ * Power Management Registers
+ */
+#define DOVE_PMU_BASE (DOVE_UNITID2PHYS(PMU)) /* 0xd0000 */
+#define DOVE_MISC_BASE (DOVE_UNITID2PHYS(PMU) + 0x0200)
+#define DOVE_GPIO_BASE (DOVE_UNITID2PHYS(PMU) + 0x0400)
+#define DOVE_PMU_BASE2 (DOVE_UNITID2PHYS(PMU) + 0x8000)
+#define DOVE_RTC_BASE (DOVE_UNITID2PHYS(PMU) + 0x8500)
+#define DOVE_PMU_SRAM_BASE (DOVE_UNITID2PHYS(PMU) + 0xc000)
+#define DOVE_PMU_SRAM_SIZE 0x800
+
+#define DOVE_PMU_SIZE 0x200
+#define DOVE_PMU_CPUSDFSCR 0x00
+#define DOVE_PMU_CPUSDFSCR_DFSEN (1 << 0)
+#define DOVE_PMU_CPUSDFSCR_CPUSLOWEN (1 << 1)
+#define DOVE_PMU_CPUSDFSCR_DDRLRATIO(x) (((x) & 0x3f) << 3)
+#define DOVE_PMU_CPUSDFSCR_CPUL2CR(x) (((x) & 0x3f) << 9)
+#define DOVE_PMU_CPUSDFSCR_CHNGPLLEN (1 << 16)
+#define DOVE_PMU_CPUSDFSSR 0x04
+#define DOVE_PMU_CPUSDFSSR_CPUSLOWMODESTTS_MASK (1 << 1)
+#define DOVE_PMU_CPUSDFSSR_CPUSLOWMODESTTS_TURBO (0 << 1)
+#define DOVE_PMU_CPUSDFSSR_CPUSLOWMODESTTS_SLOW (1 << 1)
+#define DOVE_PMU_TM_BASE 0x1c
+#define DOVE_PMU_CGCR 0x38 /* Clock Gating Control reg */
+#define DOVE_PMU_CPUCDC0R 0x44 /* CPU Clock Divider Control */
+#define DOVE_PMU_CPUCDC0R_DPRATIO(x) (((x) >> 24) & 0x3f) /* DRAM */
+#define DOVE_PMU_CPUCDC0R_XPRATIO(x) (((x) >> 16) & 0x3f) /* L2C */
+#define DOVE_PMU_CPUCDC0R_BPRATIO(x) (((x) >> 8) & 0x3f) /* AXI DS */
+#define DOVE_PMU_CPUCDC0R_PPRATIO(x) (((x) >> 0) & 0x3f) /* CPU */
+#define DOVE_PMU_PMUICR 0x50 /* PMU Interruts Cause reg */
+#define DOVE_PMU_PMUIMR 0x54 /* PMU Interruts Mask reg */
+#define DOVE_PMU_PMUI_DFSDONE (1 << 0) /* DFS Done */
+#define DOVE_PMU_PMUI_DVSDONE (1 << 1) /* DVS Done */
+#define DOVE_PMU_PMUI_THERMCOOLING (1 << 3) /* Thermal Cooling */
+#define DOVE_PMU_PMUI_THERMOVERHEAT (1 << 4) /*Thermal Overheating*/
+#define DOVE_PMU_PMUI_RTCALARM (1 << 5)
+#define DOVE_PMU_PMUI_BATTFAULT (1 << 6) /* Battery Fault */
+#define DOVE_PMU_TDC0R 0x5c /* Thermal Diode Control 0 */
+#define DOVE_PMU_TDC0R_THERMSLEEP (1 << 30) /* sleep mode */
+#define DOVE_PMU_TDC0R_THERMOTFCALB (1 << 29) /* On-The-Fly calb */
+#define DOVE_PMU_TDC0R_THERMDOUBLESLOPE (1 << 28)
+#define DOVE_PMU_TDC0R_THERMAVGNUM_MASK (0x7 << 25)
+#define DOVE_PMU_TDC0R_THERMAVGNUM_NO (0x0 << 25)
+#define DOVE_PMU_TDC0R_THERMAVGNUM_2 (0x1 << 25)
+#define DOVE_PMU_TDC0R_THERMAVGNUM_4 (0x2 << 25)
+#define DOVE_PMU_TDC0R_THERMAVGNUM_8 (0x3 << 25)
+#define DOVE_PMU_TDC0R_THERMAVGNUM_16 (0x4 << 25)
+#define DOVE_PMU_TDC0R_THERMAVGNUM_32 (0x5 << 25) /* ? */
+#define DOVE_PMU_TDC0R_THERMSELCALCAPSRC_MASK (0x7 << 20)
+#define DOVE_PMU_TDC0R_THERMREFCALCOUNT_MASK (0x1ff << 11)
+#define DOVE_PMU_TDC0R_THERMREFCALCOUNT(x) ((x) << 11)
+#define DOVE_PMU_TDC0R_THERMATEST (0x3 << 10)
+#define DOVE_PMU_TDC0R_THERMSELIREF (1 << 8)
+#define DOVE_PMU_TDC0R_THERMVBEBYPASS (1 << 7)
+#define DOVE_PMU_TDC0R_THERMSELVCAL_MASK (0x3 << 5)
+#define DOVE_PMU_TDC0R_THERMSELVCAL(x) ((x) << 5)
+#define DOVE_PMU_TDC0R_THERMTCTRIP (0x7 << 2)
+#define DOVE_PMU_TDC0R_THERMSOFTRESET (1 << 1)
+#define DOVE_PMU_TDC0R_THERMPOWERDOWN (1 << 0)
+#define DOVE_PMU_TDC1R 0x60 /* Thermal Diode Control 1 */
+
+#define DOVE_PMU_PMUCR 0x00 /* PMU Control Register */
+#define DOVE_PMU_PMUCR_MASKFIQ (1 << 28)
+#define DOVE_PMU_PMUCR_MASKIRQ (1 << 24)
+#define DOVE_PMU_PMUCR_MCSLEEPREQACK (1 << 19)
+#define DOVE_PMU_PMUCR_MCSLEEPREQ (1 << 18)
+#define DOVE_PMU_PMUCR_MCHALTREQACK (1 << 17)
+#define DOVE_PMU_PMUCR_MCHALTREQ (1 << 16)
+#define DOVE_PMU_PMUCR_DDRSELFREFEN (1 << 5)
+#define DOVE_PMU_PMUCR_STDBYPWREN (1 << 4)
+#define DOVE_PMU_PMUCR_DEEPIDLEPWREN (1 << 3)
+#define DOVE_PMU_PMUCR_EBOOKMODE (1 << 2)
+#define DOVE_PMU_PMUCR_MEMRETENTIONEN (1 << 0)
+
+#define DOVE_MISC_SAMPLE_AT_RESET0 0x14
+
+/*
+ * Audio Codec'97 (AC'97) Registers
+ */
+#define DOVE_AC97_BASE (DOVE_UNITID2PHYS(AC97)) /* 0xe0000 */
+#define DOVE_SSP_BASE (DOVE_UNITID2PHYS(AC97) + 0xc000)
+
+#endif /* _DOVEREG_H_ */
Index: src/sys/arch/arm/marvell/mvsoc_sdhc.c
diff -u /dev/null src/sys/arch/arm/marvell/mvsoc_sdhc.c:1.1
--- /dev/null Sat Jan 7 16:19:29 2017
+++ src/sys/arch/arm/marvell/mvsoc_sdhc.c Sat Jan 7 16:19:28 2017
@@ -0,0 +1,107 @@
+/* $NetBSD: mvsoc_sdhc.c,v 1.1 2017/01/07 16:19:28 kiyohara Exp $ */
+/*
+ * Copyright (c) 2016 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mvsoc_sdhc.c,v 1.1 2017/01/07 16:19:28 kiyohara Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/errno.h>
+#include <sys/malloc.h>
+#include <sys/systm.h>
+
+#include <dev/marvell/marvellreg.h>
+#include <dev/marvell/marvellvar.h>
+
+#include <dev/sdmmc/sdhcreg.h>
+#include <dev/sdmmc/sdhcvar.h>
+
+#define MVSOC_SDHC_SIZE 0x2000
+#define MVSOC_SDHC_REG_SIZE SDHC_CAPABILITIES2
+
+#define MVSOC_SDHC_MCR0 0x48
+#define MVSOC_SDHC_MCR1 0x4a
+#define MVSOC_SDHC_C1R 0x6a
+#define SDHC_C1R_CRC16_CHK_EN (1 << 2)
+
+static int mvsoc_sdhc_match(device_t, cfdata_t, void *);
+static void mvsoc_sdhc_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(mvsoc_sdhc, sizeof(struct sdhc_softc),
+ mvsoc_sdhc_match, mvsoc_sdhc_attach, NULL, NULL);
+
+static int
+mvsoc_sdhc_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct marvell_attach_args *mva = aux;
+
+ if (strcmp(mva->mva_name, match->cf_name) != 0)
+ return 0;
+ mva->mva_size = MVSOC_SDHC_SIZE;
+ return 1;
+}
+
+static void
+mvsoc_sdhc_attach(device_t parent, device_t self, void *aux)
+{
+ struct sdhc_softc *sc = device_private(self);
+ struct marvell_attach_args *mva = aux;
+ bus_space_handle_t ioh;
+ int error;
+
+ sc->sc_dev = self;
+ sc->sc_host = malloc(sizeof(*sc->sc_host), M_DEVBUF, M_WAITOK | M_ZERO);
+ sc->sc_dmat = mva->mva_dmat;
+ /* Must require the DMA. This sdhc can't 32bit access to SDHC_DATA. */
+ sc->sc_flags = SDHC_FLAG_USE_DMA;
+ sc->sc_flags |= SDHC_FLAG_EXTDMA_DMAEN;
+ sc->sc_flags |= SDHC_FLAG_NO_AUTO_STOP;
+ sc->sc_flags |= SDHC_FLAG_NO_BUSY_INTR;
+
+ aprint_naive("\n");
+ aprint_normal(": SDHC controller\n");
+
+ if (bus_space_subregion(mva->mva_iot, mva->mva_ioh,
+ mva->mva_offset, mva->mva_size, &ioh)) {
+ aprint_error_dev(self, "can't map registers\n");
+ return;
+ }
+
+ intr_establish(mva->mva_irq, IPL_VM, IST_LEVEL, sdhc_intr, sc);
+
+ bus_space_write_2(mva->mva_iot, ioh, MVSOC_SDHC_C1R,
+ bus_space_read_2(mva->mva_iot, ioh, MVSOC_SDHC_C1R) |
+ SDHC_C1R_CRC16_CHK_EN);
+
+ error = sdhc_host_found(sc, mva->mva_iot, ioh, MVSOC_SDHC_REG_SIZE);
+ if (error != 0) {
+ aprint_error_dev(self, "couldn't initialize host, error %d\n",
+ error);
+ return;
+ }
+}
Index: src/sys/arch/arm/marvell/mvsocpmu.c
diff -u /dev/null src/sys/arch/arm/marvell/mvsocpmu.c:1.1
--- /dev/null Sat Jan 7 16:19:29 2017
+++ src/sys/arch/arm/marvell/mvsocpmu.c Sat Jan 7 16:19:28 2017
@@ -0,0 +1,203 @@
+/* $NetBSD: mvsocpmu.c,v 1.1 2017/01/07 16:19:28 kiyohara Exp $ */
+/*
+ * Copyright (c) 2016 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mvsocpmu.c,v 1.1 2017/01/07 16:19:28 kiyohara Exp $");
+
+#include "opt_mvsoc.h"
+
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/errno.h>
+
+#include <dev/sysmon/sysmonvar.h>
+
+#include <arm/marvell/mvsocreg.h>
+#include <arm/marvell/mvsocvar.h>
+#include <arm/marvell/mvsocpmuvar.h>
+
+#include <dev/marvell/marvellreg.h>
+#include <dev/marvell/marvellvar.h>
+
+#define UC2UK(uc) ((uc) + 273150000)
+#define UK2UC(uk) ((uk) - 273150000)
+
+#define MVSOCPMU_TM_CSR 0x0 /* Control and Status Register */
+#define TM_CSR_TMDIS (1 << 0) /* Thermal Manager Disable */
+#define TM_CSR_THERMTEMPOUT(v) (((v) >> 1) & 0x1ff)/* Current Temperature */
+#define TM_CSR_THR(oh, c) ((((oh) & 0x1ff) << 19)|(((c) & 0x1ff) << 10))
+#define TM_CSR_COOLTHR_MASK (0x1ff << 10)
+#define TM_CSR_OVERHEATTHR_MASK (0x1ff << 19)
+#define TM_CSR_COOLTHR(v) (((v) >> 10) & 0x1ff) /* Cooling Threshold */
+#define TM_CSR_OVERHEATTHR(v) (((v) >> 19) & 0x1ff)/* Over Heat Threshold */
+#define MVSOCPMU_TM_CDR 0x4 /* Cooling Delay Register */
+#define MVSOCPMU_TM_ODR 0x8 /* Overheat Delay Register */
+
+#define MVSOCPMU_TM_READ(sc, r) \
+ bus_space_read_4((sc)->sc_iot, (sc)->sc_tmh, _TM_REG(r))
+#define MVSOCPMU_TM_WRITE(sc, r, v) \
+ bus_space_write_4((sc)->sc_iot, (sc)->sc_tmh, _TM_REG(r), (v))
+#define _TM_REG(r) MVSOCPMU_TM_ ## r
+
+static void mvsocpmu_tm_init(struct mvsocpmu_softc *);
+static void mvsocpmu_tm_refresh(struct sysmon_envsys *, envsys_data_t *);
+static void mvsocpmu_tm_get_limits(struct sysmon_envsys *, envsys_data_t *,
+ sysmon_envsys_lim_t *, uint32_t *);
+static void mvsocpmu_tm_set_limits(struct sysmon_envsys *, envsys_data_t *,
+ sysmon_envsys_lim_t *, uint32_t *);
+
+/* ARGSUSED */
+int
+mvsocpmu_match(device_t parent, struct cfdata *match, void *aux)
+{
+ struct marvell_attach_args *mva = aux;
+
+ if (strcmp(mva->mva_name, match->cf_name) != 0)
+ return 0;
+ return 1;
+}
+
+/* ARGSUSED */
+void
+mvsocpmu_attach(device_t parent, device_t self, void *aux)
+{
+ struct mvsocpmu_softc *sc = device_private(self);
+
+ aprint_naive("\n");
+ aprint_normal(": Marvell SoC Power Management Unit\n");
+
+ sc->sc_dev = self;
+
+ if (sc->sc_val2uc != NULL && sc->sc_uc2val != NULL)
+ mvsocpmu_tm_init(sc);
+}
+
+static void
+mvsocpmu_tm_init(struct mvsocpmu_softc *sc)
+{
+ uint32_t csr;
+
+ /* set default thresholds */
+ csr = MVSOCPMU_TM_READ(sc, CSR);
+ sc->sc_deflims.sel_warnmin = UC2UK(sc->sc_val2uc(TM_CSR_COOLTHR(csr)));
+ sc->sc_deflims.sel_warnmax =
+ UC2UK(sc->sc_val2uc(TM_CSR_OVERHEATTHR(csr)));
+ sc->sc_defprops = PROP_WARNMIN | PROP_WARNMAX;
+
+ sc->sc_sme = sysmon_envsys_create();
+ /* Initialize sensor data. */
+ sc->sc_sensor.units = ENVSYS_STEMP;
+ sc->sc_sensor.state = ENVSYS_SINVALID;
+ sc->sc_sensor.flags = ENVSYS_FMONLIMITS;
+ strlcpy(sc->sc_sensor.desc, device_xname(sc->sc_dev),
+ sizeof(sc->sc_sensor.desc));
+ if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) {
+ aprint_error_dev(sc->sc_dev, "Unable to attach sysmon\n");
+ sysmon_envsys_destroy(sc->sc_sme);
+ return;
+ }
+
+ /* Hook into system monitor. */
+ sc->sc_sme->sme_name = device_xname(sc->sc_dev);
+ sc->sc_sme->sme_cookie = sc;
+ sc->sc_sme->sme_refresh = mvsocpmu_tm_refresh;
+ sc->sc_sme->sme_get_limits = mvsocpmu_tm_get_limits;
+ sc->sc_sme->sme_set_limits = mvsocpmu_tm_set_limits;
+ if (sysmon_envsys_register(sc->sc_sme)) {
+ aprint_error_dev(sc->sc_dev,
+ "Unable to register with sysmon\n");
+ sysmon_envsys_destroy(sc->sc_sme);
+ }
+}
+
+static void
+mvsocpmu_tm_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
+{
+ struct mvsocpmu_softc *sc = sme->sme_cookie;
+ uint32_t csr, uc, uk;
+
+ csr = MVSOCPMU_TM_READ(sc, CSR);
+ if (csr & TM_CSR_TMDIS) {
+ sc->sc_sensor.state = ENVSYS_SINVALID;
+ return;
+ }
+ uc = sc->sc_val2uc(TM_CSR_THERMTEMPOUT(csr)); /* uC */
+ uk = UC2UK(uc); /* convert to uKelvin */
+ sc->sc_sensor.value_cur = uk;
+ sc->sc_sensor.state = ENVSYS_SVALID;
+}
+
+static void
+mvsocpmu_tm_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata,
+ sysmon_envsys_lim_t *limits, uint32_t *props)
+{
+ struct mvsocpmu_softc *sc = sme->sme_cookie;
+ uint32_t csr;
+
+ csr = MVSOCPMU_TM_READ(sc, CSR);
+ limits->sel_warnmin = UC2UK(sc->sc_val2uc(TM_CSR_COOLTHR(csr)));
+ limits->sel_warnmax = UC2UK(sc->sc_val2uc(TM_CSR_OVERHEATTHR(csr)));
+ *props = (PROP_WARNMIN | PROP_WARNMAX | PROP_DRIVER_LIMITS);
+}
+
+static void
+mvsocpmu_tm_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata,
+ sysmon_envsys_lim_t *limits, uint32_t *props)
+{
+ struct mvsocpmu_softc *sc = sme->sme_cookie;
+ uint32_t csr, mask;
+ int oh, c;
+
+ if (limits == NULL) {
+ limits = &sc->sc_deflims;
+ props = &sc->sc_defprops;
+ }
+ oh = c = 0;
+ mask = 0x0;
+ if (*props & PROP_WARNMIN) {
+ c = sc->sc_uc2val(UK2UC(limits->sel_warnmin));
+ mask |= TM_CSR_COOLTHR_MASK;
+ }
+ if (*props & PROP_WARNMAX) {
+ oh = sc->sc_uc2val(UK2UC(limits->sel_warnmax));
+ mask |= TM_CSR_OVERHEATTHR_MASK;
+ }
+ if (mask != 0) {
+ csr = MVSOCPMU_TM_READ(sc, CSR);
+ csr &= ~mask;
+ MVSOCPMU_TM_WRITE(sc, CSR, csr | TM_CSR_THR(oh, c));
+ }
+
+ /*
+ * If at least one limit is set that we can handle, and no
+ * limits are set that we cannot handle, tell sysmon that
+ * the driver will take care of monitoring the limits!
+ */
+ if (*props & (PROP_WARNMIN | PROP_WARNMAX))
+ *props |= PROP_DRIVER_LIMITS;
+ else
+ *props &= ~PROP_DRIVER_LIMITS;
+}
Index: src/sys/arch/arm/marvell/mvsocpmuvar.h
diff -u /dev/null src/sys/arch/arm/marvell/mvsocpmuvar.h:1.1
--- /dev/null Sat Jan 7 16:19:29 2017
+++ src/sys/arch/arm/marvell/mvsocpmuvar.h Sat Jan 7 16:19:28 2017
@@ -0,0 +1,48 @@
+/* $NetBSD: mvsocpmuvar.h,v 1.1 2017/01/07 16:19:28 kiyohara Exp $ */
+/*
+ * Copyright (c) 2016 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dev/sysmon/sysmonvar.h>
+
+struct mvsocpmu_softc {
+ device_t sc_dev;
+
+ bus_space_tag_t sc_iot;
+
+ /* Thermal Manager stuff */
+ bus_space_handle_t sc_tmh;
+#define MVSOC_PMU_TM_SIZE (sizeof(uint32_t) * 3)
+ int (*sc_uc2val)(int);
+ int (*sc_val2uc)(int);
+
+ struct sysmon_envsys *sc_sme;
+ envsys_data_t sc_sensor;
+ sysmon_envsys_lim_t sc_deflims;
+ uint32_t sc_defprops;
+};
+
+int mvsocpmu_match(device_t, struct cfdata *, void *);
+void mvsocpmu_attach(device_t, device_t, void *);
