Module Name: src
Committed By: palle
Date: Fri Jan 27 21:35:38 UTC 2017
Modified Files:
src/sys/arch/sparc64/sparc64: genassym.cf locore.s
Log Message:
sun4v: implement missing handling of itsb traps 0x008 and 0x009. Based on code
from OpenBSD. Tested using qemu.
To generate a diff of this commit:
cvs rdiff -u -r1.79 -r1.80 src/sys/arch/sparc64/sparc64/genassym.cf
cvs rdiff -u -r1.405 -r1.406 src/sys/arch/sparc64/sparc64/locore.s
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/sparc64/genassym.cf
diff -u src/sys/arch/sparc64/sparc64/genassym.cf:1.79 src/sys/arch/sparc64/sparc64/genassym.cf:1.80
--- src/sys/arch/sparc64/sparc64/genassym.cf:1.79 Tue May 17 19:43:28 2016
+++ src/sys/arch/sparc64/sparc64/genassym.cf Fri Jan 27 21:35:38 2017
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.79 2016/05/17 19:43:28 palle Exp $
+# $NetBSD: genassym.cf,v 1.80 2017/01/27 21:35:38 palle Exp $
#
# Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -149,6 +149,7 @@ export SUN4U_TTE_P
export SUN4U_TTE_EXEC
export SUN4V_TLB_ACCESS
export SUN4V_TLB_MODIFY
+export SUN4V_TLB_EXEC
export SUN4V_TLB_W
export SUN4V_TLB_TSB_LOCK
Index: src/sys/arch/sparc64/sparc64/locore.s
diff -u src/sys/arch/sparc64/sparc64/locore.s:1.405 src/sys/arch/sparc64/sparc64/locore.s:1.406
--- src/sys/arch/sparc64/sparc64/locore.s:1.405 Sat Jan 7 20:19:09 2017
+++ src/sys/arch/sparc64/sparc64/locore.s Fri Jan 27 21:35:38 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.405 2017/01/07 20:19:09 palle Exp $ */
+/* $NetBSD: locore.s,v 1.406 2017/01/27 21:35:38 palle Exp $ */
/*
* Copyright (c) 2006-2010 Matthew R. Green
@@ -1076,7 +1076,10 @@ _C_LABEL(trapbase_sun4v):
!
! trap level 0
!
- sun4v_trap_entry 36 ! 0x000-0x023
+ sun4v_trap_entry 8 ! 0x000-0x007
+ VTRAP(T_INST_EXCEPT, sun4v_tl0_itsb_miss) ! 0x008 - inst except
+ VTRAP(T_TEXTFAULT, sun4v_tl0_itsb_miss) ! 0x009 - inst MMU miss
+ sun4v_trap_entry 26 ! 0x00a-0x023
CLEANWIN0 ! 0x24-0x27 = clean window
sun4v_trap_entry 9 ! 0x028-0x030
VTRAP(T_DATA_MMU_MISS, sun4v_dtsb_miss) ! 0x031 = data MMU miss
@@ -2819,7 +2822,7 @@ sun4v_dtsb_miss:
btst SUN4V_TLB_ACCESS, %g4 ! Need to update access bit?
bne,pt %xcc, 2f
nop
- casxa [%g6] ASI_PHYS_CACHED, %g4, %g7 ! and write it out
+ casxa [%g6] ASI_PHYS_CACHED, %g4, %g7 ! and write it out
cmp %g4, %g7
bne,pn %xcc, 1b
or %g4, SUN4V_TLB_ACCESS, %g4 ! Update the access bit
@@ -2845,8 +2848,8 @@ sun4v_dtsb_miss:
membar #StoreStore
- STPTR %g4, [%g2 + 8] ! store TTE data
- STPTR %g1, [%g2] ! store TTE tag
+ STPTR %g4, [%g2 + 8] ! store TTE data
+ STPTR %g1, [%g2] ! store TTE tag
retry
NOTREACHED
@@ -3007,6 +3010,139 @@ sun4v_tl0_dtsb_prot:
retry
NOTREACHED
+
+sun4v_tl0_itsb_miss:
+ GET_MMFSA %g1 ! MMU Fault status area
+ add %g1, 0x8, %g3
+ LDPTRA [%g3] ASI_PHYS_CACHED, %g3 ! Instruction fault address
+ add %g1, 0x10, %g6
+ LDPTRA [%g6] ASI_PHYS_CACHED, %g6 ! Data fault context
+
+ GET_CTXBUSY %g4
+ sllx %g6, 3, %g6 ! Make it into an offset into ctxbusy
+ LDPTR [%g4 + %g6], %g4 ! Load up our page table.
+
+ srax %g3, HOLESHIFT, %g5 ! Check for valid address
+ brz,pt %g5, 0f ! Should be zero or -1
+ inc %g5 ! Make -1 -> 0
+ brnz,pn %g5, sun4v_texttrap ! Error! In hole!
+0:
+ srlx %g3, STSHIFT, %g6
+ and %g6, STMASK, %g6 ! Index into pm_segs
+ sll %g6, 3, %g6
+ add %g4, %g6, %g4
+ LDPTRA [%g4] ASI_PHYS_CACHED, %g4 ! Load page directory pointer
+
+ srlx %g3, PDSHIFT, %g6
+ and %g6, PDMASK, %g6
+ sll %g6, 3, %g6
+ brz,pn %g4, sun4v_texttrap ! NULL entry? check somewhere else
+ add %g4, %g6, %g4
+ LDPTRA [%g4] ASI_PHYS_CACHED, %g4 ! Load page table pointer
+
+ srlx %g3, PTSHIFT, %g6 ! Convert to ptab offset
+ and %g6, PTMASK, %g6
+ sll %g6, 3, %g6
+ brz,pn %g4, sun4v_texttrap ! NULL entry? check somewhere else
+ add %g4, %g6, %g6
+1:
+ LDPTRA [%g6] ASI_PHYS_CACHED, %g4 ! Fetch TTE
+ brgez,pn %g4, sun4v_texttrap ! Entry invalid? Punt
+ or %g4, SUN4V_TLB_ACCESS, %g7 ! Update the access bit
+
+ btst SUN4V_TLB_EXEC, %g4 ! Need to update exec bit?
+ bz,pn %xcc, sun4v_texttrap
+ nop
+ btst SUN4V_TLB_ACCESS, %g4 ! Need to update access bit?
+ bne,pt %xcc, 2f
+ nop
+ casxa [%g6] ASI_PHYS_CACHED, %g4, %g7 ! and write it out
+ cmp %g4, %g7
+ bne,pn %xcc, 1b
+ or %g4, SUN4V_TLB_ACCESS, %g4 ! Update the modified bit
+2:
+ GET_TSB_DMMU %g2
+
+ mov %g1, %g7
+ /* Construct TSB tag word. */
+ add %g1, 0x10, %g6
+ LDPTRA [%g6] ASI_PHYS_CACHED, %g6 ! Instruction fault context
+ mov %g3, %g1 ! Instruction fault address
+ srlx %g1, 22, %g1 ! 63..22 of virt addr
+ sllx %g6, 48, %g6 ! context_id in 63..48
+ or %g1, %g6, %g1 ! construct TTE tag
+
+ srlx %g3, PTSHIFT, %g3
+ sethi %hi(_C_LABEL(tsbsize)), %g5
+ mov 512, %g6
+ ld [%g5 + %lo(_C_LABEL(tsbsize))], %g5
+ sllx %g6, %g5, %g5 ! %g5 = 512 << tsbsize = TSBENTS
+ sub %g5, 1, %g5 ! TSBENTS -> offset
+ and %g3, %g5, %g3 ! mask out TTE index
+ sllx %g3, 4, %g3 ! TTE size is 16 bytes
+ add %g2, %g3, %g2 ! location of TTE in ci_tsb_dmmu (FIXME ci_tsb_immu?)
+
+ membar #StoreStore
+ STPTR %g4, [%g2 + 8] ! store TTE data
+ stx %g1, [%g2] ! store TTE tag
+
+ retry
+ NOTREACHED
+
+sun4v_texttrap:
+ GET_MMFSA %g3 ! MMU Fault status area
+ add %g3, 0x08, %g1
+ LDPTRA [%g1] ASI_PHYS_CACHED, %g1 ! Instruction fault address
+ add %g3, 0x10, %g2
+ LDPTRA [%g2] ASI_PHYS_CACHED, %g2 ! Instruction fault context
+
+ TRAP_SETUP(-CC64FSZ-TF_SIZE)
+
+ or %g1, %g2, %o2
+ clr %o3
+
+ rdpr %tt, %g4
+ rdpr %tstate, %g1
+ rdpr %tpc, %g2
+ rdpr %tnpc, %g3
+
+ stx %g1, [%sp + CC64FSZ + BIAS + TF_TSTATE]
+ mov %g4, %o1 ! (type)
+ stx %g2, [%sp + CC64FSZ + BIAS + TF_PC]
+ rd %y, %g5
+ stx %g3, [%sp + CC64FSZ + BIAS + TF_NPC]
+ st %g5, [%sp + CC64FSZ + BIAS + TF_Y]
+ sth %o1, [%sp + CC64FSZ + BIAS + TF_TT]! debug
+
+ ! Get back to normal globals
+ wrpr %g0, PSTATE_KERN, %pstate
+ NORMAL_GLOBALS_SUN4V
+
+ stx %g1, [%sp + CC64FSZ + BIAS + TF_G + (1*8)]
+ stx %g2, [%sp + CC64FSZ + BIAS + TF_G + (2*8)]
+ add %sp, CC64FSZ + BIAS, %o0 ! (&tf)
+ stx %g3, [%sp + CC64FSZ + BIAS + TF_G + (3*8)]
+ stx %g4, [%sp + CC64FSZ + BIAS + TF_G + (4*8)]
+ stx %g5, [%sp + CC64FSZ + BIAS + TF_G + (5*8)]
+ rdpr %pil, %g5
+ stx %g6, [%sp + CC64FSZ + BIAS + TF_G + (6*8)]
+ stx %g7, [%sp + CC64FSZ + BIAS + TF_G + (7*8)]
+ stb %g5, [%sp + CC64FSZ + BIAS + TF_PIL]
+ stb %g5, [%sp + CC64FSZ + BIAS + TF_OLDPIL]
+
+ /*
+ * Phew, ready to enable traps and call C code.
+ */
+ wrpr %g0, 0, %tl
+
+ wr %g0, ASI_PRIMARY_NOFAULT, %asi ! Restore default ASI
+ wrpr %g0, PSTATE_INTR, %pstate ! traps on again
+ call _C_LABEL(text_access_fault) ! text_access_fault(tf, type, ...)
+ nop
+
+ ba,a,pt %icc, return_from_trap
+ nop
+ NOTREACHED
/*
* End of traps for sun4v.
