Module Name: src
Committed By: flxd
Date: Tue Apr 18 14:11:42 UTC 2017
Modified Files:
src/sys/arch/shark/ofw: vlpci.c
Added Files:
src/sys/arch/shark/ofw: vlpci.h
Log Message:
First pass reducing magic numbers adding register defines.
No change to register values/writes, except VLPCI_MISC_CTL_HIADDR_DIS added.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/shark/ofw/vlpci.c
cvs rdiff -u -r0 -r1.1 src/sys/arch/shark/ofw/vlpci.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/shark/ofw/vlpci.c
diff -u src/sys/arch/shark/ofw/vlpci.c:1.7 src/sys/arch/shark/ofw/vlpci.c:1.8
--- src/sys/arch/shark/ofw/vlpci.c:1.7 Tue Apr 18 12:17:12 2017
+++ src/sys/arch/shark/ofw/vlpci.c Tue Apr 18 14:11:42 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: vlpci.c,v 1.7 2017/04/18 12:17:12 flxd Exp $ */
+/* $NetBSD: vlpci.c,v 1.8 2017/04/18 14:11:42 flxd Exp $ */
/*
* Copyright (c) 2017 Jonathan A. Kollasch
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: vlpci.c,v 1.7 2017/04/18 12:17:12 flxd Exp $");
+__KERNEL_RCSID(0, "$NetBSD: vlpci.c,v 1.8 2017/04/18 14:11:42 flxd Exp $");
#include "opt_pci.h"
#include "pci.h"
@@ -50,6 +50,17 @@ __KERNEL_RCSID(0, "$NetBSD: vlpci.c,v 1.
#include <dev/pci/pciconf.h>
#include <arm/pci_machdep.h>
+#include <shark/ofw/vlpci.h>
+
+#define VLPCI_ADDON_DEV_NO 6
+#define VLPCI_IRQ 10
+
+#define VLPCI_PCI_MEM_BASE 0x02000000
+#define VLPCI_PCI_MEM_SZ 1048576
+
+#define VLPCI_VL_MEM_BASE 0x08000000
+#define VLPCI_VL_MEM_SZ 4194304
+
static int vlpci_match(device_t, struct cfdata *, void *);
static void vlpci_attach(device_t, device_t, void *);
@@ -97,8 +108,10 @@ regwrite_1(struct vlpci_softc * const sc
{
mutex_spin_enter(&sc->sc_lock);
- bus_space_write_1(&isa_io_bs_tag, sc->sc_reg_ioh, 0, off);
- bus_space_write_1(&isa_io_bs_tag, sc->sc_reg_ioh, 1, val);
+ bus_space_write_1(&isa_io_bs_tag, sc->sc_reg_ioh, VLPCI_INTREG_IDX_OFF,
+ off);
+ bus_space_write_1(&isa_io_bs_tag, sc->sc_reg_ioh, VLPCI_INTREG_DATA_OFF,
+ val);
mutex_spin_exit(&sc->sc_lock);
}
@@ -108,8 +121,10 @@ regread_1(struct vlpci_softc * const sc,
uint8_t reg;
mutex_spin_enter(&sc->sc_lock);
- bus_space_write_1(&isa_io_bs_tag, sc->sc_reg_ioh, 0, off);
- reg = bus_space_read_1(&isa_io_bs_tag, sc->sc_reg_ioh, 1);
+ bus_space_write_1(&isa_io_bs_tag, sc->sc_reg_ioh, VLPCI_INTREG_IDX_OFF,
+ off);
+ reg = bus_space_read_1(&isa_io_bs_tag, sc->sc_reg_ioh,
+ VLPCI_INTREG_DATA_OFF);
mutex_spin_exit(&sc->sc_lock);
return reg;
}
@@ -117,14 +132,14 @@ regread_1(struct vlpci_softc * const sc,
static void
vlpci_dump_window(struct vlpci_softc *sc, int num)
{
- int regaddr = 0x87 + 3 * num;
+ int regaddr = VLPCI_PCI_WND_HIADDR_REG(num);
uint32_t addr, size;
uint8_t attr;
addr = regread_1(sc, regaddr) << 24;
addr |= regread_1(sc, regaddr + 1) << 16;
attr = regread_1(sc, regaddr + 2);
- size = 0x00010000 << ((attr & 0x1c) >> 2);
+ size = 0x00010000 << __SHIFTOUT(attr, VLPCI_PCI_WND_ATTR_SZ);
printf("memory window #%d at %08x size %08x flags %x\n", num, addr,
size, attr);
}
@@ -134,7 +149,7 @@ vlpci_map(void *t, bus_addr_t bpa, bus_s
bus_space_handle_t *bshp)
{
- *bshp = vlpci_mem_vaddr - 0x02000000 + bpa;
+ *bshp = vlpci_mem_vaddr - VLPCI_PCI_MEM_BASE + bpa;
printf("%s: %08lx -> %08lx\n", __func__, bpa, *bshp);
return(0);
}
@@ -153,6 +168,25 @@ vlpci_mmap(void *cookie, bus_addr_t addr
return arm_btop(ret);
}
+static void
+vlpci_steer_irq(struct vlpci_softc * const sc)
+{
+ const unsigned int_ctl[] = {
+ VLPCI_INT_CTL_INTA, VLPCI_INT_CTL_INTB,
+ VLPCI_INT_CTL_INTC, VLPCI_INT_CTL_INTD
+ };
+ uint8_t val;
+
+ for (size_t i = 0; i < __arraycount(int_ctl); i++) {
+ val = regread_1(sc, VLPCI_INT_CTL_REG(int_ctl[i]));
+ val &= ~VLPCI_INT_CTL_INT2IRQ(int_ctl[i]);
+ val |= VLPCI_INT_CTL_ENA(int_ctl[i]);
+ val |= __SHIFTIN(VLPCI_INT_CTL_IRQ(VLPCI_IRQ),
+ VLPCI_INT_CTL_INT2IRQ(int_ctl[i]));
+ regwrite_1(sc, VLPCI_INT_CTL_REG(int_ctl[i]), val);
+ }
+}
+
static int
vlpci_match(device_t parent, struct cfdata *match, void *aux)
{
@@ -170,6 +204,8 @@ vlpci_attach(device_t parent, device_t s
struct vlpci_softc * const sc = device_private(self);
pci_chipset_tag_t const pc = &sc->sc_pc;
struct pcibus_attach_args pba;
+ pcitag_t tag;
+ pcireg_t cmd;
aprint_normal("\n");
@@ -177,24 +213,27 @@ vlpci_attach(device_t parent, device_t s
mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);
memset(&pba, 0, sizeof(pba));
- if (bus_space_map(&isa_io_bs_tag, 0xa8, 0x2,
+ if (bus_space_map(&isa_io_bs_tag, VLPCI_INTREG_BASE, VLPCI_INTREG_SZ,
0, &sc->sc_reg_ioh) != 0) {
- aprint_error_dev(self, "failed to map 0xa8-9\n");
+ aprint_error_dev(self, "failed to map internal reg port\n");
return;
}
- if (bus_space_map(&isa_io_bs_tag, 0xcf8, 0x8,
+ if (bus_space_map(&isa_io_bs_tag, VLPCI_CFGREG_BASE, VLPCI_CFGREG_SZ,
0, &sc->sc_conf_ioh) != 0) {
- aprint_error_dev(self, "failed to map 0xcf8-f\n");
+ aprint_error_dev(self, "failed to map configuration port\n");
return;
}
/* Enable VLB/PCI bridge */
- regwrite_1(sc, 0x96, 0x18); /* enable LOCAL#, compatible mode */
- regwrite_1(sc, 0x93, 0x60); /* IOCHCK# on IOCHCK#/NMI */
- regwrite_1(sc, 0x86, 0x61); /* invert all INTx to IRQ */
- regwrite_1(sc, 0x97, 0x00); /* don't do per-INTx conversions */
- regwrite_1(sc, 0x91, 0xbb); /* enable INT[AB] to IRQ 10 */
- regwrite_1(sc, 0x90, 0xbb); /* enable INT[CD] to IRQ 10 */
+ regwrite_1(sc, VLPCI_MISC_1_REG, VLPCI_MISC_1_LOCAL_PIN |
+ VLPCI_MISC_1_COMPAT_ISA_BOFF);
+ regwrite_1(sc, VLPCI_MISC_CTL_REG, __SHIFTIN(VLPCI_MISC_CTL_HIADDR_DIS,
+ VLPCI_MISC_CTL_HIADDR) | VLPCI_MISC_CTL_IOCHCK_PIN);
+ regwrite_1(sc, VLPCI_CFG_MISC_CTL_REG,
+ __SHIFTIN(VLPCI_CFG_MISC_CTL_INT_CTL_CONV,
+ VLPCI_CFG_MISC_CTL_INT_CTL) | VLPCI_CFG_MISC_CTL_LREQI_LGNTO_PIN);
+ regwrite_1(sc, VLPCI_IRQ_MODE_REG, 0x00); /* don't do per-INTx conversions */
+ vlpci_steer_irq(sc);
/*
* XXX
* set memory size to 255MB, so the bridge knows which cycles go to RAM
@@ -203,31 +242,41 @@ vlpci_attach(device_t parent, device_t s
* ... or that's the theory. OF puts PCI BARS at 0x02000000 which
* overlaps with when we do this and pci memory access doesn't work.
*/
- regwrite_1(sc, 0x81, 0x1);
+ regwrite_1(sc, VLPCI_OBD_MEM_SZ_REG, 1);
- regwrite_1(sc, 0x82, 0x08); /* PCI dynamic acceleration decoding enable */
- regwrite_1(sc, 0x83, 0x08);
- printf("reg 0x83 %02x\n", regread_1(sc, 0x83));
+ regwrite_1(sc, VLPCI_BUF_CTL_REG, VLPCI_BUF_CTL_PCI_DYN_ACC_DEC);
+ regwrite_1(sc, VLPCI_VL_TIM_REG, VLPCI_VL_TIM_OBD_MEM_1ST_DAT);
+ printf("reg 0x83 %02x\n", regread_1(sc, VLPCI_VL_TIM_REG));
#if 1
/* program window #0 to 0x08000000 */
- regwrite_1(sc, 0x87, 0x08);
- regwrite_1(sc, 0x88, 0x00);
- regwrite_1(sc, 0x89, 0x38); /* VL, unbuffered, 4MB */
+ regwrite_1(sc, VLPCI_PCI_WND_HIADDR_REG(VLPCI_PCI_WND_NO_1),
+ VLPCI_PCI_WND_HIADDR_MEM(VLPCI_VL_MEM_BASE));
+ regwrite_1(sc, VLPCI_PCI_WND_LOADDR_REG(VLPCI_PCI_WND_NO_1),
+ VLPCI_PCI_WND_LOADDR_MEM(VLPCI_VL_MEM_BASE));
+ regwrite_1(sc, VLPCI_PCI_WND_ATTR_REG(VLPCI_PCI_WND_NO_1),
+ VLPCI_PCI_WND_ATTR_VL |
+ __SHIFTIN(VLPCI_PCI_WND_ATTR_SZ_MEM(VLPCI_VL_MEM_SZ),
+ VLPCI_PCI_WND_ATTR_SZ));
#else
- regwrite_1(sc, 0x87, 0x00);
- regwrite_1(sc, 0x88, 0x00);
- regwrite_1(sc, 0x89, 0x00);
+ regwrite_1(sc, VLPCI_PCI_WND_HIADDR_REG(VLPCI_PCI_WND_NO_1), 0x00);
+ regwrite_1(sc, VLPCI_PCI_WND_LOADDR_REG(VLPCI_PCI_WND_NO_1), 0x00);
+ regwrite_1(sc, VLPCI_PCI_WND_ATTR_REG(VLPCI_PCI_WND_NO_1), 0x00);
#endif
- vlpci_mem_paddr = 0x02000000; /* get from OF! */
+ vlpci_mem_paddr = VLPCI_PCI_MEM_BASE; /* get from OF! */
/*
* we map in 1MB at 0x02000000, so program window #1 accordingly
*/
- regwrite_1(sc, 0x8a, vlpci_mem_paddr >> 24);
- regwrite_1(sc, 0x8b, (vlpci_mem_paddr >> 16) & 0xff);
- regwrite_1(sc, 0x8c, 0x90); /* PCI, unbuffered, 1MB */
+ regwrite_1(sc, VLPCI_PCI_WND_HIADDR_REG(VLPCI_PCI_WND_NO_2),
+ VLPCI_PCI_WND_HIADDR_MEM(vlpci_mem_paddr));
+ regwrite_1(sc, VLPCI_PCI_WND_LOADDR_REG(VLPCI_PCI_WND_NO_2),
+ VLPCI_PCI_WND_LOADDR_MEM(vlpci_mem_paddr));
+ regwrite_1(sc, VLPCI_PCI_WND_ATTR_REG(VLPCI_PCI_WND_NO_2),
+ VLPCI_PCI_WND_ATTR_PCI |
+ __SHIFTIN(VLPCI_PCI_WND_ATTR_SZ_MEM(VLPCI_PCI_MEM_SZ),
+ VLPCI_PCI_WND_ATTR_SZ));
/* now map in some of the memory space */
printf("vlpci_mem_vaddr %08lx\n", vlpci_mem_vaddr);
@@ -257,11 +306,10 @@ vlpci_attach(device_t parent, device_t s
pc->pc_conf_interrupt = vlpci_pc_conf_interrupt;
/* try to assure IO space is enabled on the default device-function */
- vlpci_pc_conf_write(sc, vlpci_pc_make_tag(sc, 0, 6, 0),
- PCI_COMMAND_STATUS_REG,
- vlpci_pc_conf_read(sc, vlpci_pc_make_tag(sc, 0, 6, 0),
- PCI_COMMAND_STATUS_REG) |
- PCI_COMMAND_IO_ENABLE);
+ tag = vlpci_pc_make_tag(sc, 0, VLPCI_ADDON_DEV_NO, 0);
+ cmd = vlpci_pc_conf_read(sc, tag, PCI_COMMAND_STATUS_REG);
+ vlpci_pc_conf_write(sc, tag, PCI_COMMAND_STATUS_REG,
+ cmd | PCI_COMMAND_IO_ENABLE);
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
pba.pba_iot = &isa_io_bs_tag;
@@ -274,9 +322,9 @@ vlpci_attach(device_t parent, device_t s
isa_bus_dma_tag._ranges[0].dr_busbase,
isa_bus_dma_tag._ranges[0].dr_len);
- vlpci_dump_window(sc, 0);
- vlpci_dump_window(sc, 1);
- vlpci_dump_window(sc, 2);
+ vlpci_dump_window(sc, VLPCI_PCI_WND_NO_1);
+ vlpci_dump_window(sc, VLPCI_PCI_WND_NO_2);
+ vlpci_dump_window(sc, VLPCI_PCI_WND_NO_3);
config_found_ia(self, "pcibus", &pba, pcibusprint);
}
@@ -325,9 +373,10 @@ vlpci_pc_conf_read(void *v, pcitag_t tag
return 0xffffffff;
mutex_spin_enter(&sc->sc_lock);
- bus_space_write_4(&isa_io_bs_tag, sc->sc_conf_ioh, 0,
- 0x80000000UL|tag|offset);
- ret = bus_space_read_4(&isa_io_bs_tag, sc->sc_conf_ioh, 4);
+ bus_space_write_4(&isa_io_bs_tag, sc->sc_conf_ioh,
+ VLPCI_CFGREG_ADDR_OFF, 0x80000000UL|tag|offset);
+ ret = bus_space_read_4(&isa_io_bs_tag, sc->sc_conf_ioh,
+ VLPCI_CFGREG_DATA_OFF);
mutex_spin_exit(&sc->sc_lock);
#if 0
@@ -354,9 +403,10 @@ vlpci_pc_conf_write(void *v, pcitag_t ta
#endif
mutex_spin_enter(&sc->sc_lock);
- bus_space_write_4(&isa_io_bs_tag, sc->sc_conf_ioh, 0,
- 0x80000000UL|tag|offset);
- bus_space_write_4(&isa_io_bs_tag, sc->sc_conf_ioh, 4, val);
+ bus_space_write_4(&isa_io_bs_tag, sc->sc_conf_ioh,
+ VLPCI_CFGREG_ADDR_OFF, 0x80000000UL|tag|offset);
+ bus_space_write_4(&isa_io_bs_tag, sc->sc_conf_ioh,
+ VLPCI_CFGREG_DATA_OFF, val);
mutex_spin_exit(&sc->sc_lock);
}
@@ -372,7 +422,7 @@ vlpci_pc_intr_map(const struct pci_attac
case 2:
case 3:
case 4:
- *ih = 10;
+ *ih = VLPCI_IRQ;
return 0;
}
}
Added files:
Index: src/sys/arch/shark/ofw/vlpci.h
diff -u /dev/null src/sys/arch/shark/ofw/vlpci.h:1.1
--- /dev/null Tue Apr 18 14:11:42 2017
+++ src/sys/arch/shark/ofw/vlpci.h Tue Apr 18 14:11:42 2017
@@ -0,0 +1,280 @@
+/* $NetBSD: vlpci.h,v 1.1 2017/04/18 14:11:42 flxd Exp $ */
+
+/*-
+ * Copyright (c) 2017, Felix Deichmann
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _VLPCI_H
+#define _VLPCI_H
+
+#include <sys/param.h>
+#include <sys/cdefs.h>
+#include <sys/bitops.h>
+
+/*
+ * VT82C505 register definitions according to:
+ *
+ * VIA Technologies, Inc. "Configuration Registers of VT82C505-F", December
+ * 1994. Application Note AN-025B.
+ *
+ * VIA Technologies, Inc. "VIA VT82C505 Pentium/486 VL to PCI BRIDGE", May 1994.
+ * Datasheet.
+ */
+
+#define VLPCI_INTREG_BASE 0xa8
+#define VLPCI_INTREG_IDX_OFF 0
+#define VLPCI_INTREG_DATA_OFF 1
+#define VLPCI_INTREG_SZ 2
+
+#define VLPCI_CFGREG_BASE 0xcf8
+#define VLPCI_CFGREG_ADDR_OFF 0
+#define VLPCI_CFGREG_DATA_OFF 4
+#define VLPCI_CFGREG_SZ 8
+
+#define VLPCI_DIP_SW_REG 0x80
+#define VLPCI_DIP_SW_PCLK_CCLK __BIT(7)
+#define VLPCI_DIP_SW_SYNC_CLK __BIT(6)
+#define VLPCI_DIP_SW_IRQ14_15_PIN __BIT(5)
+#define VLPCI_DIP_SW_BLAST_PIN __BIT(4)
+#define VLPCI_DIP_SW_STRAP __BITS(7, 4)
+#define VLPCI_DIP_SW_REV_ID __BITS(3, 0)
+#define VLPCI_DIP_SW_REV_ID_D 0x1
+#define VLPCI_DIP_SW_REV_ID_E 0x2
+#define VLPCI_DIP_SW_REV_ID_F 0x3
+
+#define VLPCI_OBD_MEM_SZ_REG 0x81
+
+#define VLPCI_BUF_CTL_REG 0x82
+#define VLPCI_BUF_CTL_CPU2PCI_WR_BUF __BIT(7)
+#define VLPCI_BUF_CTL_PCI2CPU_WR_BUF __BIT(6)
+#define VLPCI_BUF_CTL_CPU2PCI_PREF_BUF __BIT(5)
+#define VLPCI_BUF_CTL_PCI2CPU_PREF_BUF __BIT(4)
+#define VLPCI_BUF_CTL_PCI_DYN_ACC_DEC __BIT(3)
+#define VLPCI_BUF_CTL_BST_B4_LST_BRDY __BIT(2)
+#define VLPCI_BUF_CTL_OBD_MEM_WR_BST __BIT(1)
+#define VLPCI_BUF_CTL_OBD_MEM_RD_BST __BIT(0)
+
+#define VLPCI_VL_TIM_REG 0x83
+#define VLPCI_VL_TIM_CPU2VL_WR_0WS __BIT(7)
+#define VLPCI_VL_TIM_LDEV_2ND_T2 __BIT(6)
+#define VLPCI_VL_TIM_TRDY2LRDY_BYP __BIT(5) /* AN-025B */
+#define VLPCI_VL_TIM_TRDY2LRDY_RESYNC __BIT(5) /* DS */
+#define VLPCI_VL_TIM_RDYRTN2TRDY_BYP __BIT(4) /* AN-025B */
+#define VLPCI_VL_TIM_RDYRTN2TRDY_RESYNC __BIT(4) /* DS */
+#define VLPCI_VL_TIM_OBD_MEM_1ST_DAT __BIT(3)
+#define VLPCI_VL_TIM_CPU2PCI_WR_BST __BIT(2)
+#define VLPCI_VL_TIM_PADS_DIS __BIT(1)
+#define VLPCI_VL_TIM_TST_MODE __BIT(0)
+
+#define VLPCI_PCI_TIM_REG 0x84
+#define VLPCI_PCI_TIM_SLV_LOCK __BIT(7)
+#define VLPCI_PCI_TIM_RTY_CNT_64 __BIT(6)
+#define VLPCI_PCI_TIM_RTY_DEADL_ERR_REP __BIT(5)
+#define VLPCI_PCI_TIM_RTY_STS_OCCU __BIT(4)
+#define VLPCI_PCI_TIM_CPU2PCI_FAST_B2B __BIT(3)
+#define VLPCI_PCI_TIM_FAST_FRAME __BIT(2)
+#define VLPCI_PCI_TIM_DEVSEL_DEC __BITS(1, 0)
+#define VLPCI_PCI_TIM_DEVSEL_DEC_SUBTR 0x3
+#define VLPCI_PCI_TIM_DEVSEL_DEC_SLOW 0x2
+#define VLPCI_PCI_TIM_DEVSEL_DEC_MDM 0x1
+#define VLPCI_PCI_TIM_DEVSEL_DEC_FAST 0x0
+
+#define VLPCI_PCI_ARB_REG 0x85
+#define VLPCI_PCI_ARB_FAIR __BIT(7)
+#define VLPCI_PCI_ARB_FRAME __BIT(6)
+#define VLPCI_PCI_ARB_CPU_TIM_SLT __BITS(5, 4)
+#define VLPCI_PCI_ARB_CPU_TIM_SLT_32CLK 0x3
+#define VLPCI_PCI_ARB_CPU_TIM_SLT_16CLK 0x2
+#define VLPCI_PCI_ARB_CPU_TIM_SLT_8CLK 0x1
+#define VLPCI_PCI_ARB_CPU_TIM_SLT_4CLK 0x0
+#define VLPCI_PCI_ARB_PCI_MST_TMO __BITS(3, 0)
+#define VLPCI_PCI_ARB_PCI_MST_TMO_DIS 0x0
+#define VLPCI_PCI_ARB_PCI_MST_TMO_1X32CLK 0x1
+#define VLPCI_PCI_ARB_PCI_MST_TMO_2X32CLK 0x2
+#define VLPCI_PCI_ARB_PCI_MST_TMO_3X32CLK 0x3
+#define VLPCI_PCI_ARB_PCI_MST_TMO_4X32CLK 0x4
+#define VLPCI_PCI_ARB_PCI_MST_TMO_5X32CLK 0x5
+#define VLPCI_PCI_ARB_PCI_MST_TMO_6X32CLK 0x6
+#define VLPCI_PCI_ARB_PCI_MST_TMO_7X32CLK 0x7
+#define VLPCI_PCI_ARB_PCI_MST_TMO_8X32CLK 0x8
+#define VLPCI_PCI_ARB_PCI_MST_TMO_9X32CLK 0x9
+#define VLPCI_PCI_ARB_PCI_MST_TMO_10X32CLK 0xa
+#define VLPCI_PCI_ARB_PCI_MST_TMO_11X32CLK 0xb
+#define VLPCI_PCI_ARB_PCI_MST_TMO_12X32CLK 0xc
+#define VLPCI_PCI_ARB_PCI_MST_TMO_13X32CLK 0xd
+#define VLPCI_PCI_ARB_PCI_MST_TMO_14X32CLK 0xe
+#define VLPCI_PCI_ARB_PCI_MST_TMO_15X32CLK 0xf
+
+#define VLPCI_CFG_MISC_CTL_REG 0x86
+#define VLPCI_CFG_MISC_CTL_PCI_CFG_MECHN_2 __BIT(7)
+#define VLPCI_CFG_MISC_CTL_INT_CTL __BITS(5, 6)
+#define VLPCI_CFG_MISC_CTL_INT_CTL_TRSP 0x0
+#define VLPCI_CFG_MISC_CTL_INT_CTL_CONV_INTL 0x1
+#define VLPCI_CFG_MISC_CTL_INT_CTL_TRSP_INV 0x2
+#define VLPCI_CFG_MISC_CTL_INT_CTL_CONV 0x3
+#define VLPCI_CFG_MISC_CTL_TST_MODE __BIT(4)
+#define VLPCI_CFG_MISC_CTL_SERR_NMI __BIT(3)
+#define VLPCI_CFG_MISC_CTL_SERR_STS __BIT(2)
+#define VLPCI_CFG_MISC_CTL_PCI_MST_BRK_TMR __BIT(1)
+#define VLPCI_CFG_MISC_CTL_LREQI_LGNTO_PIN __BIT(0)
+
+#define VLPCI_PCI_WND_NO_1 1
+#define VLPCI_PCI_WND_NO_2 2
+#define VLPCI_PCI_WND_NO_3 3
+
+#define VLPCI_PCI_WND_HIADDR_REG(no) (0x87 + 3 * ((no) - 1))
+#define VLPCI_PCI_WND_HIADDR_IO(x) (((x) >> 8) & 0xff)
+#define VLPCI_PCI_WND_HIADDR_MEM(x) (((x) >> 24) & 0xff)
+
+#define VLPCI_PCI_WND_LOADDR_REG(no) (0x88 + 3 * ((no) - 1))
+#define VLPCI_PCI_WND_LOADDR_IO(x) (((x) >> 0) & 0xff)
+#define VLPCI_PCI_WND_LOADDR_MEM(x) (((x) >> 16) & 0xff)
+
+/*
+ * Window attributes differ significantly between AN-025B (PCI windows only,
+ * memory and I/O) and DS (PCI and VL windows, memory only).
+ */
+#define VLPCI_PCI_WND_ATTR_REG(no) (0x89 + 3 * ((no) - 1))
+#define VLPCI_PCI_WND_ATTR_ENA __BIT(7) /* AN-025B */
+#define VLPCI_PCI_WND_ATTR_PCI __BIT(7) /* DS */
+#define VLPCI_PCI_WND_ATTR_WR_BUF __BIT(6)
+#define VLPCI_PCI_WND_ATTR_IO __BIT(5) /* AN-025B */
+#define VLPCI_PCI_WND_ATTR_VL __BIT(5) /* DS */
+#define VLPCI_PCI_WND_ATTR_SZ __BITS(4, 2)
+/* I/O size only present in AN-025B. */
+#define VLPCI_PCI_WND_ATTR_SZ_IO_4 0x0
+#define VLPCI_PCI_WND_ATTR_SZ_IO_8 0x1
+#define VLPCI_PCI_WND_ATTR_SZ_IO_16 0x2
+#define VLPCI_PCI_WND_ATTR_SZ_IO_32 0x3
+#define VLPCI_PCI_WND_ATTR_SZ_IO_64 0x4
+#define VLPCI_PCI_WND_ATTR_SZ_IO_128 0x5
+#define VLPCI_PCI_WND_ATTR_SZ_IO_256 0x6
+#define VLPCI_PCI_WND_ATTR_SZ_IO_512 0x7
+#define VLPCI_PCI_WND_ATTR_SZ_IO(b) ilog2((b) >> 2)
+#define VLPCI_PCI_WND_ATTR_SZ_MEM_64K 0x0
+#define VLPCI_PCI_WND_ATTR_SZ_MEM_128K 0x1
+#define VLPCI_PCI_WND_ATTR_SZ_MEM_256K 0x2
+#define VLPCI_PCI_WND_ATTR_SZ_MEM_512K 0x3
+#define VLPCI_PCI_WND_ATTR_SZ_MEM_1M 0x4
+#define VLPCI_PCI_WND_ATTR_SZ_MEM_2M 0x5
+#define VLPCI_PCI_WND_ATTR_SZ_MEM_4M 0x6
+#define VLPCI_PCI_WND_ATTR_SZ_MEM_8M 0x7
+#define VLPCI_PCI_WND_ATTR_SZ_MEM(b) ilog2((b) >> 16)
+
+#define VLPCI_INT_CTL_REG(int) (0x90 + (int) / 8)
+#define VLPCI_INT_CTL_ENA(int) __BIT((int) % 8 + 3)
+#define VLPCI_INT_CTL_INT2IRQ(int) __BITS((int) % 8 + 2, (int) % 8)
+#define VLPCI_INT_CTL_INTB 12
+#define VLPCI_INT_CTL_INTA 8
+#define VLPCI_INT_CTL_INTD 4
+#define VLPCI_INT_CTL_INTC 0
+#define VLPCI_INT_CTL_IRQ_NONE 0x0
+#define VLPCI_INT_CTL_IRQ5 0x1
+#define VLPCI_INT_CTL_IRQ9 0x2
+#define VLPCI_INT_CTL_IRQ10 0x3
+#define VLPCI_INT_CTL_IRQ11 0x4
+#define VLPCI_INT_CTL_IRQ14 0x5
+#define VLPCI_INT_CTL_IRQ15 0x6
+#define VLPCI_INT_CTL_IRQ(irq) \
+ (((irq) == 5) ? VLPCI_INT_CTL_IRQ5 : \
+ ((irq) == 9) ? VLPCI_INT_CTL_IRQ9 : \
+ ((irq) == 10) ? VLPCI_INT_CTL_IRQ10 : \
+ ((irq) == 11) ? VLPCI_INT_CTL_IRQ11 : \
+ ((irq) == 14) ? VLPCI_INT_CTL_IRQ14 : \
+ ((irq) == 15) ? VLPCI_INT_CTL_IRQ15 : \
+ VLPCI_INT_CTL_IRQ_NONE)
+
+#define VLPCI_ACC_ISA_CYC_REG 0x92
+#define VLPCI_ACC_ISA_CYC_A0000 __BIT(7)
+#define VLPCI_ACC_ISA_CYC_B0000 __BIT(6)
+#define VLPCI_ACC_ISA_CYC_C0000 __BIT(5)
+#define VLPCI_ACC_ISA_CYC_C8000 __BIT(4)
+#define VLPCI_ACC_ISA_CYC_D0000 __BIT(3)
+#define VLPCI_ACC_ISA_CYC_D8000 __BIT(2)
+#define VLPCI_ACC_ISA_CYC_E0000 __BIT(1)
+#define VLPCI_ACC_ISA_CYC_E8000 __BIT(0)
+/* F0000h to FFFFFh is always accelerated ISA cycle. */
+
+#define VLPCI_MISC_CTL_REG 0x93
+#define VLPCI_MISC_CTL_HIADDR (__BITS(7, 6) | __BIT(4))
+#define VLPCI_MISC_CTL_HIADDR_CA26_ABV 0x0 /* 0b00x0 */
+#define VLPCI_MISC_CTL_HIADDR_CA27_ABV 0x4 /* 0b01x0 */
+#define VLPCI_MISC_CTL_HIADDR_CA28_ABV 0x8 /* 0b10x0 */
+#define VLPCI_MISC_CTL_HIADDR_CA29_ABV 0xc /* 0b11x0 */
+#define VLPCI_MISC_CTL_HIADDR_CA30_ABV 0x1 /* 0b00x1 */
+#define VLPCI_MISC_CTL_HIADDR_CA31_ABV 0x5 /* 0b01x1 */
+#define VLPCI_MISC_CTL_HIADDR_DIS 0xd /* 0b11x1 */
+#define VLPCI_MISC_CTL_IOCHCK_PIN __BIT(5)
+#define VLPCI_MISC_CTL_2ND_VL_IDE __BIT(3)
+#define VLPCI_MISC_CTL_1ST_VL_IDE __BIT(2)
+#define VLPCI_MISC_CTL_OBD_IO_ACC_ISA __BIT(0)
+
+#define VLPCI_ACC_PCI_64K_WND_REG 0x94
+#define VLPCI_ACC_PCI_64K_WND_A0000 __BIT(7)
+#define VLPCI_ACC_PCI_64K_WND_B0000 __BIT(6)
+#define VLPCI_ACC_PCI_64K_WND_C0000 __BIT(5)
+#define VLPCI_ACC_PCI_64K_WND_C8000 __BIT(4)
+#define VLPCI_ACC_PCI_64K_WND_D0000 __BIT(3)
+#define VLPCI_ACC_PCI_64K_WND_D8000 __BIT(2)
+#define VLPCI_ACC_PCI_64K_WND_E0000 __BIT(1)
+#define VLPCI_ACC_PCI_64K_WND_E8000 __BIT(0)
+
+#define VLPCI_ACC_PCI_32K_WND_REG 0x95
+#define VLPCI_ACC_PCI_32K_WND_A0000 __BIT(7)
+#define VLPCI_ACC_PCI_32K_WND_A8000 __BIT(6)
+#define VLPCI_ACC_PCI_32K_WND_B0000 __BIT(5)
+#define VLPCI_ACC_PCI_32K_WND_B8000 __BIT(4)
+
+#define VLPCI_MISC_1_REG 0x96
+#define VLPCI_MISC_1_DYN_DEC_MEM_WR __BIT(7)
+#define VLPCI_MISC_1_RTY_TMO_ACTION __BIT(6)
+#define VLPCI_MISC_1_DYN_DEC_DIS __BIT(5)
+#define VLPCI_MISC_1_LOCAL_PIN __BIT(4)
+#define VLPCI_MISC_1_COMPAT_ISA_BOFF __BIT(3)
+#define VLPCI_MISC_1_IRQ_IDLE_LOW __BIT(2)
+#define VLPCI_MISC_1_PCI_MST_1WS_WR __BIT(1)
+#define VLPCI_MISC_1_PCI_SLV_1WS_BST_WR __BIT(0)
+
+/* Individual INT[ABCD] mode control from VT82C505-E on. */
+#define VLPCI_IRQ_MODE_REG 0x97
+#define VLPCI_IRQ_MODE_CTL(i) __BITS((i) + 1, (i))
+#define VLPCI_IRQ_MODE_CTL_INTA 6
+#define VLPCI_IRQ_MODE_CTL_INTB 4
+#define VLPCI_IRQ_MODE_CTL_INTC 2
+#define VLPCI_IRQ_MODE_CTL_INTD 0
+
+#define VLPCI_OBD_MEM_EADDR_REG 0x98
+#define VLPCI_OBD_MEM_EADDR_CA32_CA28 __BITS(4, 0)
+
+#define VLPCI_MISC_2_REG 0x99
+#define VLPCI_MISC_2_BYTE_MRG __BIT(7)
+#define VLPCI_MISC_2_ENH_BYTE_MRG __BIT(6)
+#define VLPCI_MISC_2_DYN_PCI_BST __BIT(5)
+#define VLPCI_MISC_2_RTY_FAIL_POP_1_DAT __BIT(4)
+#define VLPCI_MISC_2_2WAY_DYN_DEC __BIT(3)
+#define VLPCI_MISC_2_ISAREQ_1CLK_DLY __BIT(1)
+#define VLPCI_MISC_2_ADS_1CLK_DLY __BIT(0)
+
+#endif /* !defined(_VLPCI_H) */
