Module Name: src
Committed By: jmcneill
Date: Thu May 25 23:26:48 UTC 2017
Modified Files:
src/sys/arch/arm/nvidia: files.tegra tegra_soc.c tegra_var.h
Added Files:
src/sys/arch/arm/nvidia: soc_tegra210.c
Log Message:
Chip detection and MP spinup code for Tegra210
To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/arm/nvidia/files.tegra
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/nvidia/soc_tegra210.c
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/nvidia/tegra_soc.c
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/arm/nvidia/tegra_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/nvidia/files.tegra
diff -u src/sys/arch/arm/nvidia/files.tegra:1.35 src/sys/arch/arm/nvidia/files.tegra:1.36
--- src/sys/arch/arm/nvidia/files.tegra:1.35 Sat Apr 29 11:01:51 2017
+++ src/sys/arch/arm/nvidia/files.tegra Thu May 25 23:26:48 2017
@@ -1,4 +1,4 @@
-# $NetBSD: files.tegra,v 1.35 2017/04/29 11:01:51 jmcneill Exp $
+# $NetBSD: files.tegra,v 1.36 2017/05/25 23:26:48 jmcneill Exp $
#
# Configuration info for NVIDIA Tegra ARM Peripherals
#
@@ -27,6 +27,9 @@ device tegra124cpu
attach tegra124cpu at fdt with tegra124_cpu
file arch/arm/nvidia/tegra124_cpu.c tegra124_cpu
+# Tegra T210 (X1) support
+file arch/arm/nvidia/soc_tegra210.c soc_tegra210
+
# Interrupt controller
device tegralic
attach tegralic at fdt with tegra_lic
@@ -161,4 +164,6 @@ defparam opt_tegra.h MEMSIZE
# SOC parameters
defflag opt_tegra.h SOC_TEGRAK1
+defflag opt_tegra.h SOC_TEGRAX1
defflag opt_tegra.h SOC_TEGRA124: SOC_TEGRAK1
+defflag opt_tegra.h SOC_TEGRA210: SOC_TEGRAX1
Index: src/sys/arch/arm/nvidia/tegra_soc.c
diff -u src/sys/arch/arm/nvidia/tegra_soc.c:1.10 src/sys/arch/arm/nvidia/tegra_soc.c:1.11
--- src/sys/arch/arm/nvidia/tegra_soc.c:1.10 Sat Apr 22 23:53:24 2017
+++ src/sys/arch/arm/nvidia/tegra_soc.c Thu May 25 23:26:48 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_soc.c,v 1.10 2017/04/22 23:53:24 jmcneill Exp $ */
+/* $NetBSD: tegra_soc.c,v 1.11 2017/05/25 23:26:48 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <[email protected]>
@@ -30,7 +30,7 @@
#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.10 2017/04/22 23:53:24 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.11 2017/05/25 23:26:48 jmcneill Exp $");
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/param.h>
@@ -99,6 +99,11 @@ tegra_mpinit(void)
tegra124_mpinit();
break;
#endif
+#ifdef SOC_TEGRA210
+ case CHIP_ID_TEGRA210:
+ tegra210_mpinit();
+ break;
+#endif
default:
panic("Unsupported SOC ID %#x", tegra_chip_id());
}
@@ -127,6 +132,7 @@ tegra_chip_name(void)
switch (tegra_chip_id()) {
case CHIP_ID_TEGRA124: return "Tegra K1 (T124)";
case CHIP_ID_TEGRA132: return "Tegra K1 (T132)";
+ case CHIP_ID_TEGRA210: return "Tegra X1 (T210)";
default: return "Unknown Tegra SoC";
}
}
Index: src/sys/arch/arm/nvidia/tegra_var.h
diff -u src/sys/arch/arm/nvidia/tegra_var.h:1.34 src/sys/arch/arm/nvidia/tegra_var.h:1.35
--- src/sys/arch/arm/nvidia/tegra_var.h:1.34 Thu May 25 23:12:59 2017
+++ src/sys/arch/arm/nvidia/tegra_var.h Thu May 25 23:26:48 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_var.h,v 1.34 2017/05/25 23:12:59 jmcneill Exp $ */
+/* $NetBSD: tegra_var.h,v 1.35 2017/05/25 23:26:48 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <[email protected]>
@@ -107,6 +107,9 @@ void tegra_cpufreq_register(const struct
#if defined(SOC_TEGRA124)
void tegra124_mpinit(void);
#endif
+#if defined(SOC_TEGRA210)
+void tegra210_mpinit(void);
+#endif
static void inline
tegra_reg_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh,
Added files:
Index: src/sys/arch/arm/nvidia/soc_tegra210.c
diff -u /dev/null src/sys/arch/arm/nvidia/soc_tegra210.c:1.1
--- /dev/null Thu May 25 23:26:48 2017
+++ src/sys/arch/arm/nvidia/soc_tegra210.c Thu May 25 23:26:48 2017
@@ -0,0 +1,81 @@
+/* $NetBSD: soc_tegra210.c,v 1.1 2017/05/25 23:26:48 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_tegra.h"
+#include "opt_multiprocessor.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: soc_tegra210.c,v 1.1 2017/05/25 23:26:48 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/cpufunc.h>
+
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra_pmcreg.h>
+#include <arm/nvidia/tegra_var.h>
+
+#define EVP_RESET_VECTOR_0_REG 0x100
+
+void
+tegra210_mpinit(void)
+{
+#if defined(MULTIPROCESSOR)
+ extern void cortex_mpstart(void);
+ bus_space_tag_t bst = &armv7_generic_bs_tag;
+ bus_space_handle_t bsh;
+
+ bus_space_subregion(bst, tegra_ppsb_bsh,
+ TEGRA_EVP_OFFSET, TEGRA_EVP_SIZE, &bsh);
+
+ arm_cpu_max = 4;
+
+ bus_space_write_4(bst, bsh, EVP_RESET_VECTOR_0_REG,
+ (uint32_t)cortex_mpstart);
+ bus_space_barrier(bst, bsh, EVP_RESET_VECTOR_0_REG, 4,
+ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+ uint32_t started = 0;
+
+ tegra_pmc_power(PMC_PARTID_CPU1, true); started |= __BIT(1);
+ tegra_pmc_power(PMC_PARTID_CPU2, true); started |= __BIT(2);
+ tegra_pmc_power(PMC_PARTID_CPU3, true); started |= __BIT(3);
+
+ for (u_int i = 0x10000000; i > 0; i--) {
+ arm_dmb();
+ if (arm_cpu_hatched == started)
+ break;
+ }
+#endif
+}
