Module Name: src
Committed By: jmcneill
Date: Sun Jun 11 00:13:15 UTC 2017
Modified Files:
src/sys/arch/arm/samsung: exynos_reg.h
Log Message:
Avoid divide-by-zero for unconfigured PLLs
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/samsung/exynos_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/samsung/exynos_reg.h
diff -u src/sys/arch/arm/samsung/exynos_reg.h:1.14 src/sys/arch/arm/samsung/exynos_reg.h:1.15
--- src/sys/arch/arm/samsung/exynos_reg.h:1.14 Sat Jun 10 15:13:18 2017
+++ src/sys/arch/arm/samsung/exynos_reg.h Sun Jun 11 00:13:15 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos_reg.h,v 1.14 2017/06/10 15:13:18 jmcneill Exp $ */
+/* $NetBSD: exynos_reg.h,v 1.15 2017/06/11 00:13:15 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -124,7 +124,8 @@
#define PLL_CON0_P __BITS( 8,13) /* PLL P divide value */
#define PLL_CON0_S __BITS( 0, 2) /* PLL S divide value */
-#define PLL_PMS2FREQ(F, M, P, S) (((M)*(F))/((P)*(1<<(S))))
+#define PLL_PMS2FREQ(F, M, P, S) \
+ ((P) == 0 ? 0 : (((M)*(F))/((P)*(1<<(S)))))
#define PLL_FREQ(f, v) PLL_PMS2FREQ( \
(f),\
__SHIFTOUT((v), PLL_CON0_M),\
