Module Name: src
Committed By: snj
Date: Wed Jul 26 15:22:37 UTC 2017
Modified Files:
src/external/broadcom/rpi-firmware/dist [netbsd-7]: bootcode.bin
fixup.dat fixup_cd.dat start.elf start_cd.elf
src/sys/arch/arm/arm32 [netbsd-7]: cpu.c
src/sys/arch/arm/broadcom [netbsd-7]: bcm2835_bsc.c bcm2835_plcom.c
src/sys/arch/arm/cortex [netbsd-7]: gtmr.c
src/sys/arch/arm/include [netbsd-7]: armreg.h vfpreg.h
src/sys/arch/arm/vfp [netbsd-7]: vfp_init.c
src/sys/arch/evbarm/rpi [netbsd-7]: rpi_machdep.c vcprop.h
Log Message:
Pull up following revision(s) (requested by jmcneill in ticket #1435):
sys/arch/arm/arm32/cpu.c: 1.113 via patch
sys/arch/arm/broadcom/bcm2835_bsc.c: 1.6 via patch
sys/arch/arm/broadcom/bcm2835_plcom.c: 1.4 via patch
sys/arch/arm/cortex/gtmr.c: 1.18 via patch
sys/arch/arm/include/armreg.h: 1.110 via patch
sys/arch/arm/include/vfpreg.h: 1.15 via patch
sys/arch/arm/vfp/vfp_init.c: 1.50 via patch
sys/arch/evbarm/rpi/rpi_machdep.c: 1.59, 1.70-1.72 via patch
sys/arch/evbarm/rpi/vcprop.h: 1.16
Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs.
While I'm here add some A57/A72 info as well.
My RPI3 works with FB console - the uart needs some help with its clocks.
--
Do invalidate the cache as RPI2 build with Clang can't fetch the memory
config otherwise.
--
Use the VC property mailbox to request the UART clock rate and use it
appropriately
Newer firmwares use 48MHz
--
Disable BSC0 on Raspberry Pi 3 and Zero W boards.
--
Interrupts are enabled before the timer is configured. Ensure that the
timer is disabled when attaching so it doesn't go crazy between the time
interrupts are enabled and clocks are initialized. My RPI3 makes it
multi-user now.
--
Enable UART0 (PL011) on GPIO header for Raspberry Pi 3 / Zero W
To generate a diff of this commit:
cvs rdiff -u -r1.5.2.2 -r1.5.2.3 \
src/external/broadcom/rpi-firmware/dist/bootcode.bin \
src/external/broadcom/rpi-firmware/dist/fixup.dat \
src/external/broadcom/rpi-firmware/dist/fixup_cd.dat \
src/external/broadcom/rpi-firmware/dist/start.elf \
src/external/broadcom/rpi-firmware/dist/start_cd.elf
cvs rdiff -u -r1.104.4.1 -r1.104.4.2 src/sys/arch/arm/arm32/cpu.c
cvs rdiff -u -r1.2.4.1 -r1.2.4.2 src/sys/arch/arm/broadcom/bcm2835_bsc.c
cvs rdiff -u -r1.1 -r1.1.18.1 src/sys/arch/arm/broadcom/bcm2835_plcom.c
cvs rdiff -u -r1.8.2.2 -r1.8.2.3 src/sys/arch/arm/cortex/gtmr.c
cvs rdiff -u -r1.97.2.2 -r1.97.2.3 src/sys/arch/arm/include/armreg.h
cvs rdiff -u -r1.13 -r1.13.4.1 src/sys/arch/arm/include/vfpreg.h
cvs rdiff -u -r1.41.2.2 -r1.41.2.3 src/sys/arch/arm/vfp/vfp_init.c
cvs rdiff -u -r1.43.2.6 -r1.43.2.7 src/sys/arch/evbarm/rpi/rpi_machdep.c
cvs rdiff -u -r1.9 -r1.9.2.1 src/sys/arch/evbarm/rpi/vcprop.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/external/broadcom/rpi-firmware/dist/bootcode.bin
Binary files are different
Index: src/external/broadcom/rpi-firmware/dist/fixup.dat
Binary files are different
Index: src/external/broadcom/rpi-firmware/dist/fixup_cd.dat
Binary files are different
Index: src/external/broadcom/rpi-firmware/dist/start.elf
Binary files are different
Index: src/external/broadcom/rpi-firmware/dist/start_cd.elf
Binary files are different
Index: src/sys/arch/arm/arm32/cpu.c
diff -u src/sys/arch/arm/arm32/cpu.c:1.104.4.1 src/sys/arch/arm/arm32/cpu.c:1.104.4.2
--- src/sys/arch/arm/arm32/cpu.c:1.104.4.1 Mon Apr 6 01:57:57 2015
+++ src/sys/arch/arm/arm32/cpu.c Wed Jul 26 15:22:36 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.104.4.1 2015/04/06 01:57:57 snj Exp $ */
+/* $NetBSD: cpu.c,v 1.104.4.2 2017/07/26 15:22:36 snj Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.104.4.1 2015/04/06 01:57:57 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.104.4.2 2017/07/26 15:22:36 snj Exp $");
#include <sys/systm.h>
#include <sys/conf.h>
@@ -511,6 +511,14 @@ const struct cpuidtab cpuids[] = {
pN_steppings, "7A" },
{ CPU_ID_CORTEXA15R3, CPU_CLASS_CORTEX, "Cortex-A15 r3",
pN_steppings, "7A" },
+ { CPU_ID_CORTEXA53R0, CPU_CLASS_CORTEX, "Cortex-A53 r0",
+ pN_steppings, "8A" },
+ { CPU_ID_CORTEXA57R0, CPU_CLASS_CORTEX, "Cortex-A57 r0",
+ pN_steppings, "8A" },
+ { CPU_ID_CORTEXA57R1, CPU_CLASS_CORTEX, "Cortex-A57 r1",
+ pN_steppings, "8A" },
+ { CPU_ID_CORTEXA72R0, CPU_CLASS_CORTEX, "Cortex-A72 r0",
+ pN_steppings, "8A" },
{ CPU_ID_MV88SV581X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV581x",
generic_steppings },
Index: src/sys/arch/arm/broadcom/bcm2835_bsc.c
diff -u src/sys/arch/arm/broadcom/bcm2835_bsc.c:1.2.4.1 src/sys/arch/arm/broadcom/bcm2835_bsc.c:1.2.4.2
--- src/sys/arch/arm/broadcom/bcm2835_bsc.c:1.2.4.1 Thu Sep 11 13:46:49 2014
+++ src/sys/arch/arm/broadcom/bcm2835_bsc.c Wed Jul 26 15:22:36 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm2835_bsc.c,v 1.2.4.1 2014/09/11 13:46:49 martin Exp $ */
+/* $NetBSD: bcm2835_bsc.c,v 1.2.4.2 2017/07/26 15:22:36 snj Exp $ */
/*
* Copyright (c) 2012 Jonathan A. Kollasch
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bcm2835_bsc.c,v 1.2.4.1 2014/09/11 13:46:49 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bcm2835_bsc.c,v 1.2.4.2 2017/07/26 15:22:36 snj Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -99,8 +99,10 @@ bsciic_attach(device_t parent, device_t
{
struct bsciic_softc * const sc = device_private(self);
struct amba_attach_args * const aaa = aux;
+ prop_dictionary_t prop = device_properties(self);
struct i2cbus_attach_args iba;
u_int bscunit = ~0;
+ bool disable = false;
static ONCE_DECL(control);
switch (aaa->aaa_addr) {
@@ -112,6 +114,13 @@ bsciic_attach(device_t parent, device_t
break;
}
+ prop_dictionary_get_bool(prop, "disable", &disable);
+ if (disable) {
+ aprint_naive(": disabled\n");
+ aprint_normal(": disabled\n");
+ return;
+ }
+
aprint_naive("\n");
aprint_normal(": BSC%u\n", bscunit);
Index: src/sys/arch/arm/broadcom/bcm2835_plcom.c
diff -u src/sys/arch/arm/broadcom/bcm2835_plcom.c:1.1 src/sys/arch/arm/broadcom/bcm2835_plcom.c:1.1.18.1
--- src/sys/arch/arm/broadcom/bcm2835_plcom.c:1.1 Thu Jul 26 06:21:57 2012
+++ src/sys/arch/arm/broadcom/bcm2835_plcom.c Wed Jul 26 15:22:36 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm2835_plcom.c,v 1.1 2012/07/26 06:21:57 skrll Exp $ */
+/* $NetBSD: bcm2835_plcom.c,v 1.1.18.1 2017/07/26 15:22:36 snj Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
/* Interface to plcom (PL011) serial driver. */
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bcm2835_plcom.c,v 1.1 2012/07/26 06:21:57 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bcm2835_plcom.c,v 1.1.18.1 2017/07/26 15:22:36 snj Exp $");
#include <sys/types.h>
#include <sys/device.h>
@@ -69,11 +69,19 @@ static void
bcm2835_plcom_attach(device_t parent, device_t self, void *aux)
{
struct plcom_softc *sc = device_private(self);
+ prop_dictionary_t dict = device_properties(self);
struct amba_attach_args *aaa = aux;
void *ih;
sc->sc_dev = self;
sc->sc_frequency = BCM2835_UART0_CLK;
+
+ /* Fetch the UART clock frequency from property if set. */
+ prop_number_t frequency = prop_dictionary_get(dict, "frequency");
+ if (frequency != NULL) {
+ sc->sc_frequency = prop_number_integer_value(frequency);
+ }
+
sc->sc_hwflags = PLCOM_HW_TXFIFO_DISABLE;
sc->sc_swflags = 0;
sc->sc_set_mcr = NULL;
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.8.2.2 src/sys/arch/arm/cortex/gtmr.c:1.8.2.3
--- src/sys/arch/arm/cortex/gtmr.c:1.8.2.2 Mon Apr 6 01:55:53 2015
+++ src/sys/arch/arm/cortex/gtmr.c Wed Jul 26 15:22:36 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.8.2.2 2015/04/06 01:55:53 snj Exp $ */
+/* $NetBSD: gtmr.c,v 1.8.2.3 2017/07/26 15:22:36 snj Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.8.2.2 2015/04/06 01:55:53 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.8.2.3 2017/07/26 15:22:36 snj Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -147,6 +147,10 @@ gtmr_attach(device_t parent, device_t se
gtmr_timecounter.tc_frequency = sc->sc_freq;
tc_init(>mr_timecounter);
+
+ /* Disable the timer until we are ready */
+ armreg_cntv_ctl_write(0);
+ armreg_cntp_ctl_write(0);
}
void
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.97.2.2 src/sys/arch/arm/include/armreg.h:1.97.2.3
--- src/sys/arch/arm/include/armreg.h:1.97.2.2 Thu Dec 8 07:41:14 2016
+++ src/sys/arch/arm/include/armreg.h Wed Jul 26 15:22:36 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.97.2.2 2016/12/08 07:41:14 snj Exp $ */
+/* $NetBSD: armreg.h,v 1.97.2.3 2017/07/26 15:22:36 snj Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -226,12 +226,20 @@
#define CPU_ID_CORTEXA9R4 0x414fc090
#define CPU_ID_CORTEXA15R2 0x412fc0f0
#define CPU_ID_CORTEXA15R3 0x413fc0f0
-#define CPU_ID_CORTEX_P(n) ((n & 0xff0ff000) == 0x410fc000)
+#define CPU_ID_CORTEXA53R0 0x410fd030
+#define CPU_ID_CORTEXA57R0 0x410fd070
+#define CPU_ID_CORTEXA57R1 0x411fd070
+#define CPU_ID_CORTEXA72R0 0x410fd080
+
+#define CPU_ID_CORTEX_P(n) ((n & 0xff0fe000) == 0x410fc000)
#define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050)
#define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070)
#define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080)
#define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090)
#define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0)
+#define CPU_ID_CORTEX_A53_P(n) ((n & 0xff0ff0f0) == 0x410fd030)
+#define CPU_ID_CORTEX_A57_P(n) ((n & 0xff0ff0f0) == 0x410fd070)
+#define CPU_ID_CORTEX_A72_P(n) ((n & 0xff0ff0f0) == 0x410fd080)
#define CPU_ID_SA110 0x4401a100
#define CPU_ID_SA1100 0x4401a110
#define CPU_ID_TI925T 0x54029250
Index: src/sys/arch/arm/include/vfpreg.h
diff -u src/sys/arch/arm/include/vfpreg.h:1.13 src/sys/arch/arm/include/vfpreg.h:1.13.4.1
--- src/sys/arch/arm/include/vfpreg.h:1.13 Tue Mar 18 07:03:22 2014
+++ src/sys/arch/arm/include/vfpreg.h Wed Jul 26 15:22:36 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: vfpreg.h,v 1.13 2014/03/18 07:03:22 matt Exp $ */
+/* $NetBSD: vfpreg.h,v 1.13.4.1 2017/07/26 15:22:36 snj Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@@ -64,6 +64,7 @@
#define FPU_VFP_CORTEXA8 0x410330c0
#define FPU_VFP_CORTEXA9 0x41033090
#define FPU_VFP_CORTEXA15 0x410330f0
+#define FPU_VFP_CORTEXA53 0x41034030
#define FPU_VFP_MV88SV58XX 0x56022090
#define VFP_FPEXC_EX 0x80000000 /* EXception status bit */
Index: src/sys/arch/arm/vfp/vfp_init.c
diff -u src/sys/arch/arm/vfp/vfp_init.c:1.41.2.2 src/sys/arch/arm/vfp/vfp_init.c:1.41.2.3
--- src/sys/arch/arm/vfp/vfp_init.c:1.41.2.2 Thu Mar 26 08:53:48 2015
+++ src/sys/arch/arm/vfp/vfp_init.c Wed Jul 26 15:22:37 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: vfp_init.c,v 1.41.2.2 2015/03/26 08:53:48 snj Exp $ */
+/* $NetBSD: vfp_init.c,v 1.41.2.3 2017/07/26 15:22:37 snj Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@@ -94,6 +94,7 @@ load_vfpregs(const struct vfpreg *fregs)
case FPU_VFP_CORTEXA8:
case FPU_VFP_CORTEXA9:
case FPU_VFP_CORTEXA15:
+ case FPU_VFP_CORTEXA53:
#endif
load_vfpregs_hi(fregs->vfp_regs);
#ifdef CPU_ARM11
@@ -115,6 +116,7 @@ save_vfpregs(struct vfpreg *fregs)
case FPU_VFP_CORTEXA8:
case FPU_VFP_CORTEXA9:
case FPU_VFP_CORTEXA15:
+ case FPU_VFP_CORTEXA53:
#endif
save_vfpregs_hi(fregs->vfp_regs);
#ifdef CPU_ARM11
@@ -312,6 +314,7 @@ vfp_attach(struct cpu_info *ci)
case FPU_VFP_CORTEXA8:
case FPU_VFP_CORTEXA9:
case FPU_VFP_CORTEXA15:
+ case FPU_VFP_CORTEXA53:
if (armreg_cpacr_read() & CPACR_V7_ASEDIS) {
model = "VFP 4.0+";
} else {
Index: src/sys/arch/evbarm/rpi/rpi_machdep.c
diff -u src/sys/arch/evbarm/rpi/rpi_machdep.c:1.43.2.6 src/sys/arch/evbarm/rpi/rpi_machdep.c:1.43.2.7
--- src/sys/arch/evbarm/rpi/rpi_machdep.c:1.43.2.6 Fri Feb 26 22:52:53 2016
+++ src/sys/arch/evbarm/rpi/rpi_machdep.c Wed Jul 26 15:22:37 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: rpi_machdep.c,v 1.43.2.6 2016/02/26 22:52:53 snj Exp $ */
+/* $NetBSD: rpi_machdep.c,v 1.43.2.7 2017/07/26 15:22:37 snj Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rpi_machdep.c,v 1.43.2.6 2016/02/26 22:52:53 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rpi_machdep.c,v 1.43.2.7 2017/07/26 15:22:37 snj Exp $");
#include "opt_arm_debug.h"
#include "opt_bcm283x.h"
@@ -73,6 +73,7 @@ __KERNEL_RCSID(0, "$NetBSD: rpi_machdep.
#include <arm/broadcom/bcm2835var.h>
#include <arm/broadcom/bcm2835_pmvar.h>
#include <arm/broadcom/bcm2835_mbox.h>
+#include <arm/broadcom/bcm2835_gpio_subr.h>
#include <evbarm/rpi/vcio.h>
#include <evbarm/rpi/vcpm.h>
@@ -130,6 +131,8 @@ static void rpi_device_register(device_t
#define RPI_FB_HEIGHT 720
#endif
+int uart_clk = BCM2835_UART0_CLK;
+
#define PLCONADDR BCM2835_UART0_BASE
#ifndef CONSDEVNAME
@@ -176,6 +179,36 @@ static struct plcom_instance rpi_pi = {
static struct __aligned(16) {
struct vcprop_buffer_hdr vb_hdr;
+ struct vcprop_tag_clockrate vbt_uartclockrate;
+ struct vcprop_tag_boardrev vbt_boardrev;
+ struct vcprop_tag end;
+} vb_uart = {
+ .vb_hdr = {
+ .vpb_len = sizeof(vb_uart),
+ .vpb_rcode = VCPROP_PROCESS_REQUEST,
+ },
+ .vbt_uartclockrate = {
+ .tag = {
+ .vpt_tag = VCPROPTAG_GET_CLOCKRATE,
+ .vpt_len = VCPROPTAG_LEN(vb_uart.vbt_uartclockrate),
+ .vpt_rcode = VCPROPTAG_REQUEST
+ },
+ .id = VCPROP_CLK_UART
+ },
+ .vbt_boardrev = {
+ .tag = {
+ .vpt_tag = VCPROPTAG_GET_BOARDREVISION,
+ .vpt_len = VCPROPTAG_LEN(vb_uart.vbt_boardrev),
+ .vpt_rcode = VCPROPTAG_REQUEST
+ },
+ },
+ .end = {
+ .vpt_tag = VCPROPTAG_NULL
+ }
+};
+
+static struct __aligned(16) {
+ struct vcprop_buffer_hdr vb_hdr;
struct vcprop_tag_fwrev vbt_fwrev;
struct vcprop_tag_boardmodel vbt_boardmodel;
struct vcprop_tag_boardrev vbt_boardrev;
@@ -377,6 +410,39 @@ extern void bcmgenfb_ddb_trap_callback(i
#endif
static void
+rpi_uartinit(void)
+{
+ const paddr_t pa = BCM2835_PERIPHERALS_BUS_TO_PHYS(BCM2835_ARMMBOX_BASE);
+ const bus_space_tag_t iot = &bcm2835_bs_tag;
+ const bus_space_handle_t ioh = BCM2835_IOPHYSTOVIRT(pa);
+ uint32_t res;
+
+ bcm2835_mbox_write(iot, ioh, BCMMBOX_CHANARM2VC, KERN_VTOPHYS(&vb_uart));
+
+ bcm2835_mbox_read(iot, ioh, BCMMBOX_CHANARM2VC, &res);
+
+ cpu_dcache_inv_range((vaddr_t)&vb_uart, sizeof(vb_uart));
+
+ if (vcprop_tag_success_p(&vb_uart.vbt_boardrev.tag) &&
+ (vb_uart.vbt_boardrev.rev & VCPROP_REV_ENCFLAG) != 0) {
+ const uint32_t rev = vb_uart.vbt_boardrev.rev;
+ switch (__SHIFTOUT(rev, VCPROP_REV_MODEL)) {
+ case RPI_MODEL_B_PI3:
+ case RPI_MODEL_ZERO_W:
+ /* Enable UART0 (PL011) on GPIO header */
+ bcm2835gpio_function_select(14, BCM2835_GPIO_ALT0);
+ bcm2835gpio_function_select(15, BCM2835_GPIO_ALT0);
+ break;
+ }
+ }
+
+ if (vcprop_tag_success_p(&vb_uart.vbt_uartclockrate.tag))
+ uart_clk = vb_uart.vbt_uartclockrate.rate;
+}
+
+
+
+static void
rpi_bootparams(void)
{
const paddr_t pa = BCM2835_PERIPHERALS_BUS_TO_PHYS(BCM2835_ARMMBOX_BASE);
@@ -407,13 +473,7 @@ rpi_bootparams(void)
bcm2835_mbox_read(iot, ioh, BCMMBOX_CHANARM2VC, &res);
- /*
- * No need to invalid the cache as the memory has never been referenced
- * by the ARM.
- *
- * cpu_dcache_inv_range((vaddr_t)&vb, sizeof(vb));
- *
- */
+ cpu_dcache_inv_range((vaddr_t)&vb, sizeof(vb));
if (!vcprop_buffer_success_p(&vb.vb_hdr)) {
bootconfig.dramblocks = 1;
@@ -583,6 +643,8 @@ initarm(void *arg)
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
+ rpi_uartinit();
+
consinit();
/* Talk to the user */
@@ -691,7 +753,7 @@ consinit(void)
*/
rpi_pi.pi_iobase = consaddr;
- plcomcnattach(&rpi_pi, plcomcnspeed, BCM2835_UART0_CLK,
+ plcomcnattach(&rpi_pi, plcomcnspeed, uart_clk,
plcomcnmode, PLCOMCNUNIT);
#endif
@@ -715,7 +777,7 @@ static kgdb_port_init(void)
rpi_pi.pi_iobase = consaddr;
- res = plcom_kgdb_attach(&rpi_pi, KGDB_DEVRATE, BCM2835_UART0_CLK,
+ res = plcom_kgdb_attach(&rpi_pi, KGDB_DEVRATE, uart_clk,
KGDB_CONMODE, KGDB_PLCOMUNIT);
if (res)
panic("KGDB uart can not be initialized, err=%d.", res);
@@ -902,6 +964,12 @@ rpi_device_register(device_t dev, void *
}
#endif
+ if (device_is_a(dev, "plcom") &&
+ vcprop_tag_success_p(&vb_uart.vbt_uartclockrate.tag) &&
+ vb_uart.vbt_uartclockrate.rate > 0) {
+ prop_dictionary_set_uint32(dict,
+ "frequency", vb_uart.vbt_uartclockrate.rate);
+ }
if (device_is_a(dev, "bcmdmac") &&
vcprop_tag_success_p(&vb.vbt_dmachan.tag)) {
prop_dictionary_set_uint32(dict,
Index: src/sys/arch/evbarm/rpi/vcprop.h
diff -u src/sys/arch/evbarm/rpi/vcprop.h:1.9 src/sys/arch/evbarm/rpi/vcprop.h:1.9.2.1
--- src/sys/arch/evbarm/rpi/vcprop.h:1.9 Fri Jul 25 11:39:34 2014
+++ src/sys/arch/evbarm/rpi/vcprop.h Wed Jul 26 15:22:37 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: vcprop.h,v 1.9 2014/07/25 11:39:34 jmcneill Exp $ */
+/* $NetBSD: vcprop.h,v 1.9.2.1 2017/07/26 15:22:37 snj Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -124,6 +124,28 @@ struct vcprop_tag_boardrev {
uint32_t rev;
} ;
+#define VCPROP_REV_PCBREV __BITS(3,0)
+#define VCPROP_REV_MODEL __BITS(11,4)
+#define RPI_MODEL_A 0
+#define RPI_MODEL_B 1
+#define RPI_MODEL_A_PLUS 2
+#define RPI_MODEL_B_PLUS 3
+#define RPI_MODEL_B_PI2 4
+#define RPI_MODEL_ALPHA 5
+#define RPI_MODEL_COMPUTE 6
+#define RPI_MODEL_ZERO 7
+#define RPI_MODEL_B_PI3 8
+#define RPI_MODEL_COMPUTE_PI3 9
+#define RPI_MODEL_ZERO_W 10
+#define VCPROP_REV_PROCESSOR __BITS(15,12)
+#define RPI_PROCESSOR_BCM2835 0
+#define RPI_PROCESSOR_BCM2836 1
+#define RPI_PROCESSOR_BCM2837 2
+#define VCPROP_REV_MANUF __BITS(19,16)
+#define VCPROP_REV_MEMSIZE __BITS(22,20)
+#define VCPROP_REV_ENCFLAG __BIT(23)
+#define VCPROP_REV_WARRANTY __BITS(25,24)
+
struct vcprop_tag_macaddr {
struct vcprop_tag tag;
uint64_t addr;
