Module Name: src
Committed By: jmcneill
Date: Thu Sep 7 01:07:04 UTC 2017
Modified Files:
src/sys/arch/arm/sunxi: files.sunxi sunxi_emac.c sunxi_mmc.c
sunxi_usbphy.c
src/sys/arch/evbarm/conf: SUNXI
Added Files:
src/sys/arch/arm/sunxi: sun50i_a64_ccu.c sun50i_a64_ccu.h
Log Message:
Add support for Allwinner A64 SoCs.
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/arm/sunxi/files.sunxi
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/sunxi/sun50i_a64_ccu.c \
src/sys/arch/arm/sunxi/sun50i_a64_ccu.h
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/sunxi/sunxi_emac.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/sunxi/sunxi_mmc.c \
src/sys/arch/arm/sunxi/sunxi_usbphy.c
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/evbarm/conf/SUNXI
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/sunxi/files.sunxi
diff -u src/sys/arch/arm/sunxi/files.sunxi:1.21 src/sys/arch/arm/sunxi/files.sunxi:1.22
--- src/sys/arch/arm/sunxi/files.sunxi:1.21 Sun Aug 27 19:17:54 2017
+++ src/sys/arch/arm/sunxi/files.sunxi Thu Sep 7 01:07:04 2017
@@ -1,4 +1,4 @@
-# $NetBSD: files.sunxi,v 1.21 2017/08/27 19:17:54 jmcneill Exp $
+# $NetBSD: files.sunxi,v 1.22 2017/09/07 01:07:04 jmcneill Exp $
#
# Configuration info for Allwinner sunxi family SoCs
#
@@ -47,6 +47,11 @@ device sun8ih3ccu: sunxi_ccu
attach sun8ih3ccu at fdt with sunxi_h3_ccu
file arch/arm/sunxi/sun8i_h3_ccu.c sunxi_h3_ccu
+# CCU (A64)
+device sun50ia64ccu: sunxi_ccu
+attach sun50ia64ccu at fdt with sunxi_a64_ccu
+file arch/arm/sunxi/sun50i_a64_ccu.c sunxi_a64_ccu
+
# Misc. clock resets
device sunxiresets
attach sunxiresets at fdt with sunxi_resets
Index: src/sys/arch/arm/sunxi/sunxi_emac.c
diff -u src/sys/arch/arm/sunxi/sunxi_emac.c:1.4 src/sys/arch/arm/sunxi/sunxi_emac.c:1.5
--- src/sys/arch/arm/sunxi/sunxi_emac.c:1.4 Fri Jul 7 21:40:56 2017
+++ src/sys/arch/arm/sunxi/sunxi_emac.c Thu Sep 7 01:07:04 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_emac.c,v 1.4 2017/07/07 21:40:56 jmcneill Exp $ */
+/* $NetBSD: sunxi_emac.c,v 1.5 2017/09/07 01:07:04 jmcneill Exp $ */
/*-
* Copyright (c) 2016-2017 Jared McNeill <jmcne...@invisible.ca>
@@ -33,7 +33,7 @@
#include "opt_net_mpsafe.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c,v 1.4 2017/07/07 21:40:56 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c,v 1.5 2017/09/07 01:07:04 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -131,11 +131,13 @@ static int sunxi_emac_tx_interval = TX_I
enum sunxi_emac_type {
EMAC_A83T = 1,
EMAC_H3,
+ EMAC_A64,
};
static const struct of_compat_data compat_data[] = {
{ "allwinner,sun8i-a83t-emac", EMAC_A83T },
{ "allwinner,sun8i-h3-emac", EMAC_H3 },
+ { "allwinner,sun50i-a64-emac", EMAC_A64 },
{ NULL }
};
Index: src/sys/arch/arm/sunxi/sunxi_mmc.c
diff -u src/sys/arch/arm/sunxi/sunxi_mmc.c:1.5 src/sys/arch/arm/sunxi/sunxi_mmc.c:1.6
--- src/sys/arch/arm/sunxi/sunxi_mmc.c:1.5 Sun Aug 27 17:53:10 2017
+++ src/sys/arch/arm/sunxi/sunxi_mmc.c Thu Sep 7 01:07:04 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_mmc.c,v 1.5 2017/08/27 17:53:10 jmcneill Exp $ */
+/* $NetBSD: sunxi_mmc.c,v 1.6 2017/09/07 01:07:04 jmcneill Exp $ */
/*-
* Copyright (c) 2014-2017 Jared McNeill <jmcne...@invisible.ca>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.5 2017/08/27 17:53:10 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.6 2017/09/07 01:07:04 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -167,6 +167,7 @@ CFATTACH_DECL_NEW(sunxi_mmc, sizeof(stru
static const char * const compatible[] = {
"allwinner,sun5i-a13-mmc",
"allwinner,sun7i-a20-mmc",
+ "allwinner,sun50i-a64-mmc",
NULL
};
Index: src/sys/arch/arm/sunxi/sunxi_usbphy.c
diff -u src/sys/arch/arm/sunxi/sunxi_usbphy.c:1.5 src/sys/arch/arm/sunxi/sunxi_usbphy.c:1.6
--- src/sys/arch/arm/sunxi/sunxi_usbphy.c:1.5 Fri Aug 25 12:28:51 2017
+++ src/sys/arch/arm/sunxi/sunxi_usbphy.c Thu Sep 7 01:07:04 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_usbphy.c,v 1.5 2017/08/25 12:28:51 jmcneill Exp $ */
+/* $NetBSD: sunxi_usbphy.c,v 1.6 2017/09/07 01:07:04 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_usbphy.c,v 1.5 2017/08/25 12:28:51 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_usbphy.c,v 1.6 2017/09/07 01:07:04 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -57,12 +57,14 @@ enum sunxi_usbphy_type {
USBPHY_A13,
USBPHY_A31,
USBPHY_H3,
+ USBPHY_A64,
};
static const struct of_compat_data compat_data[] = {
{ "allwinner,sun5i-a13-usb-phy", USBPHY_A13 },
{ "allwinner,sun6i-a31-usb-phy", USBPHY_A31 },
{ "allwinner,sun8i-h3-usb-phy", USBPHY_H3 },
+ { "allwinner,sun50i-a64-usb-phy", USBPHY_A64 },
{ NULL }
};
Index: src/sys/arch/evbarm/conf/SUNXI
diff -u src/sys/arch/evbarm/conf/SUNXI:1.26 src/sys/arch/evbarm/conf/SUNXI:1.27
--- src/sys/arch/evbarm/conf/SUNXI:1.26 Tue Aug 29 09:55:25 2017
+++ src/sys/arch/evbarm/conf/SUNXI Thu Sep 7 01:07:04 2017
@@ -1,5 +1,5 @@
#
-# $NetBSD: SUNXI,v 1.26 2017/08/29 09:55:25 jmcneill Exp $
+# $NetBSD: SUNXI,v 1.27 2017/09/07 01:07:04 jmcneill Exp $
#
# Allwinner sunxi family
#
@@ -48,13 +48,17 @@ makeoptions DTS="
sun8i-h3-orangepi-plus2e.dts
"
+options MULTIPROCESSOR
+
options CPU_CORTEXA7
options CPU_CORTEXA8
+options CPU_CORTEXA53
+
options SOC_SUN5I_A13
options SOC_SUN6I_A31
options SOC_SUN8I_A83T
options SOC_SUN8I_H3
-options MULTIPROCESSOR
+options SOC_SUN50I_A64
pseudo-device openfirm # /dev/openfirm
@@ -88,6 +92,7 @@ sun5ia13ccu* at fdt? pass 4 # A13 CCU
sun6ia31ccu* at fdt? pass 4 # A31 CCU
sun8ia83tccu* at fdt? pass 4 # A83T CCU
sun8ih3ccu* at fdt? pass 4 # H3 CCU
+sun50ia64ccu* at fdt? pass 4 # A64 CCU
sunxiresets* at fdt? pass 1 # Misc. clock resets
sunxigates* at fdt? pass 1 # Misc. clock gates
Added files:
Index: src/sys/arch/arm/sunxi/sun50i_a64_ccu.c
diff -u /dev/null src/sys/arch/arm/sunxi/sun50i_a64_ccu.c:1.1
--- /dev/null Thu Sep 7 01:07:04 2017
+++ src/sys/arch/arm/sunxi/sun50i_a64_ccu.c Thu Sep 7 01:07:04 2017
@@ -0,0 +1,349 @@
+/* $NetBSD: sun50i_a64_ccu.c,v 1.1 2017/09/07 01:07:04 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.1 2017/09/07 01:07:04 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/sunxi/sunxi_ccu.h>
+#include <arm/sunxi/sun50i_a64_ccu.h>
+
+#define PLL_CPUX_CTRL_REG 0x000
+#define PLL_AUDIO_CTRL_REG 0x008
+#define PLL_PERIPH0_CTRL_REG 0x028
+#define PLL_PERIPH1_CTRL_REG 0x02c
+#define AHB1_APB1_CFG_REG 0x054
+#define APB2_CFG_REG 0x058
+#define AHB2_CFG_REG 0x05c
+#define AHB2_CLK_CFG __BITS(1,0)
+#define AHB2_CLK_CFG_PLL_PERIPH0_2 1
+#define BUS_CLK_GATING_REG0 0x060
+#define BUS_CLK_GATING_REG1 0x064
+#define BUS_CLK_GATING_REG2 0x068
+#define BUS_CLK_GATING_REG3 0x06c
+#define BUS_CLK_GATING_REG4 0x070
+#define SDMMC0_CLK_REG 0x088
+#define SDMMC1_CLK_REG 0x08c
+#define SDMMC2_CLK_REG 0x090
+#define USBPHY_CFG_REG 0x0cc
+#define DRAM_CFG_REG 0x0f4
+#define MBUS_RST_REG 0x0fc
+#define AC_DIG_CLK_REG 0x140
+#define BUS_SOFT_RST_REG0 0x2c0
+#define BUS_SOFT_RST_REG1 0x2c4
+#define BUS_SOFT_RST_REG2 0x2c8
+#define BUS_SOFT_RST_REG3 0x2d0
+#define BUS_SOFT_RST_REG4 0x2d8
+
+static int sun50i_a64_ccu_match(device_t, cfdata_t, void *);
+static void sun50i_a64_ccu_attach(device_t, device_t, void *);
+
+static const char * const compatible[] = {
+ "allwinner,sun50i-a64-ccu",
+ NULL
+};
+
+CFATTACH_DECL_NEW(sunxi_a64_ccu, sizeof(struct sunxi_ccu_softc),
+ sun50i_a64_ccu_match, sun50i_a64_ccu_attach, NULL, NULL);
+
+static struct sunxi_ccu_reset sun50i_a64_ccu_resets[] = {
+ SUNXI_CCU_RESET(A64_RST_USB_PHY0, USBPHY_CFG_REG, 0),
+ SUNXI_CCU_RESET(A64_RST_USB_PHY1, USBPHY_CFG_REG, 1),
+ SUNXI_CCU_RESET(A64_RST_USB_HSIC, USBPHY_CFG_REG, 2),
+
+ SUNXI_CCU_RESET(A64_RST_DRAM, DRAM_CFG_REG, 31),
+
+ SUNXI_CCU_RESET(A64_RST_MBUS, MBUS_RST_REG, 31),
+
+ SUNXI_CCU_RESET(A64_RST_BUS_MIPI_DSI, BUS_SOFT_RST_REG0, 1),
+ SUNXI_CCU_RESET(A64_RST_BUS_CE, BUS_SOFT_RST_REG0, 5),
+ SUNXI_CCU_RESET(A64_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6),
+ SUNXI_CCU_RESET(A64_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8),
+ SUNXI_CCU_RESET(A64_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9),
+ SUNXI_CCU_RESET(A64_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10),
+ SUNXI_CCU_RESET(A64_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13),
+ SUNXI_CCU_RESET(A64_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14),
+ SUNXI_CCU_RESET(A64_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17),
+ SUNXI_CCU_RESET(A64_RST_BUS_TS, BUS_SOFT_RST_REG0, 18),
+ SUNXI_CCU_RESET(A64_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19),
+ SUNXI_CCU_RESET(A64_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20),
+ SUNXI_CCU_RESET(A64_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21),
+ SUNXI_CCU_RESET(A64_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23),
+ SUNXI_CCU_RESET(A64_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24),
+ SUNXI_CCU_RESET(A64_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25),
+ SUNXI_CCU_RESET(A64_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 26),
+ SUNXI_CCU_RESET(A64_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 27),
+
+ SUNXI_CCU_RESET(A64_RST_BUS_VE, BUS_SOFT_RST_REG1, 0),
+ SUNXI_CCU_RESET(A64_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3),
+ SUNXI_CCU_RESET(A64_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4),
+ SUNXI_CCU_RESET(A64_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5),
+ SUNXI_CCU_RESET(A64_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8),
+ SUNXI_CCU_RESET(A64_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10),
+ SUNXI_CCU_RESET(A64_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11),
+ SUNXI_CCU_RESET(A64_RST_BUS_DE, BUS_SOFT_RST_REG1, 12),
+ SUNXI_CCU_RESET(A64_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20),
+ SUNXI_CCU_RESET(A64_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21),
+ SUNXI_CCU_RESET(A64_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22),
+ SUNXI_CCU_RESET(A64_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31),
+
+ SUNXI_CCU_RESET(A64_RST_BUS_LVDS, BUS_SOFT_RST_REG2, 0),
+
+ SUNXI_CCU_RESET(A64_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0),
+ SUNXI_CCU_RESET(A64_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1),
+ SUNXI_CCU_RESET(A64_RST_BUS_THS, BUS_SOFT_RST_REG3, 8),
+ SUNXI_CCU_RESET(A64_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12),
+ SUNXI_CCU_RESET(A64_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13),
+ SUNXI_CCU_RESET(A64_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14),
+
+ SUNXI_CCU_RESET(A64_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0),
+ SUNXI_CCU_RESET(A64_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1),
+ SUNXI_CCU_RESET(A64_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2),
+ SUNXI_CCU_RESET(A64_RST_BUS_SCR, BUS_SOFT_RST_REG4, 5),
+ SUNXI_CCU_RESET(A64_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16),
+ SUNXI_CCU_RESET(A64_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17),
+ SUNXI_CCU_RESET(A64_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18),
+ SUNXI_CCU_RESET(A64_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19),
+};
+
+static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" };
+static const char *ahb2_parents[] = { "ahb1", "pll_periph0" };
+static const char *apb1_parents[] = { "ahb1" };
+static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" };
+static const char *mod_parents[] = { "hosc", "pll_periph0", "pll_periph1" };
+
+static struct sunxi_ccu_clk sun50i_a64_ccu_clks[] = {
+ SUNXI_CCU_NKMP(A64_CLK_PLL_PERIPH0, "pll_periph0", "hosc",
+ PLL_PERIPH0_CTRL_REG, /* reg */
+ __BITS(12,8), /* n */
+ __BITS(5,4), /* k */
+ 0, /* m */
+ __BITS(17,16), /* p */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NKMP_DIVIDE_BY_TWO),
+
+ SUNXI_CCU_PREDIV(A64_CLK_AHB1, "ahb1", ahb1_parents,
+ AHB1_APB1_CFG_REG, /* reg */
+ __BITS(7,6), /* prediv */
+ __BIT(3), /* prediv_sel */
+ __BITS(5,4), /* div */
+ __BITS(13,12), /* sel */
+ SUNXI_CCU_PREDIV_POWER_OF_TWO),
+
+ SUNXI_CCU_PREDIV(A64_CLK_AHB2, "ahb2", ahb2_parents,
+ AHB2_CFG_REG, /* reg */
+ 0, /* prediv */
+ __BIT(1), /* prediv_sel */
+ 0, /* div */
+ __BITS(1,0), /* sel */
+ SUNXI_CCU_PREDIV_DIVIDE_BY_TWO),
+
+ SUNXI_CCU_DIV(A64_CLK_APB1, "apb1", apb1_parents,
+ AHB1_APB1_CFG_REG, /* reg */
+ __BITS(9,8), /* div */
+ 0, /* sel */
+ SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE),
+
+ SUNXI_CCU_NM(A64_CLK_APB2, "apb2", apb2_parents,
+ APB2_CFG_REG, /* reg */
+ __BITS(17,16), /* n */
+ __BITS(4,0), /* m */
+ __BITS(25,24), /* sel */
+ 0, /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO),
+
+ SUNXI_CCU_NM(A64_CLK_MMC0, "mmc0", mod_parents,
+ SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+ SUNXI_CCU_NM(A64_CLK_MMC1, "mmc1", mod_parents,
+ SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+ SUNXI_CCU_NM(A64_CLK_MMC2, "mmc2", mod_parents,
+ SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+
+ SUNXI_CCU_GATE(A64_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1",
+ BUS_CLK_GATING_REG0, 1),
+ SUNXI_CCU_GATE(A64_CLK_BUS_CE, "bus-ce", "ahb1",
+ BUS_CLK_GATING_REG0, 5),
+ SUNXI_CCU_GATE(A64_CLK_BUS_DMA, "bus-dma", "ahb1",
+ BUS_CLK_GATING_REG0, 6),
+ SUNXI_CCU_GATE(A64_CLK_BUS_MMC0, "bus-mmc0", "ahb1",
+ BUS_CLK_GATING_REG0, 8),
+ SUNXI_CCU_GATE(A64_CLK_BUS_MMC1, "bus-mmc1", "ahb1",
+ BUS_CLK_GATING_REG0, 9),
+ SUNXI_CCU_GATE(A64_CLK_BUS_MMC2, "bus-mmc2", "ahb1",
+ BUS_CLK_GATING_REG0, 10),
+ SUNXI_CCU_GATE(A64_CLK_BUS_NAND, "bus-nand", "ahb1",
+ BUS_CLK_GATING_REG0, 13),
+ SUNXI_CCU_GATE(A64_CLK_BUS_DRAM, "bus-dram", "ahb1",
+ BUS_CLK_GATING_REG0, 14),
+ SUNXI_CCU_GATE(A64_CLK_BUS_EMAC, "bus-emac", "ahb2",
+ BUS_CLK_GATING_REG0, 17),
+ SUNXI_CCU_GATE(A64_CLK_BUS_TS, "bus-ts", "ahb1",
+ BUS_CLK_GATING_REG0, 18),
+ SUNXI_CCU_GATE(A64_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1",
+ BUS_CLK_GATING_REG0, 19),
+ SUNXI_CCU_GATE(A64_CLK_BUS_SPI0, "bus-spi0", "ahb1",
+ BUS_CLK_GATING_REG0, 20),
+ SUNXI_CCU_GATE(A64_CLK_BUS_SPI1, "bus-spi1", "ahb1",
+ BUS_CLK_GATING_REG0, 21),
+ SUNXI_CCU_GATE(A64_CLK_BUS_OTG, "bus-otg", "ahb1",
+ BUS_CLK_GATING_REG0, 23),
+ SUNXI_CCU_GATE(A64_CLK_BUS_EHCI0, "bus-ehci0", "ahb1",
+ BUS_CLK_GATING_REG0, 24),
+ SUNXI_CCU_GATE(A64_CLK_BUS_EHCI1, "bus-ehci1", "ahb2",
+ BUS_CLK_GATING_REG0, 25),
+ SUNXI_CCU_GATE(A64_CLK_BUS_OHCI0, "bus-ohci0", "ahb1",
+ BUS_CLK_GATING_REG0, 26),
+ SUNXI_CCU_GATE(A64_CLK_BUS_OHCI1, "bus-ohci1", "ahb2",
+ BUS_CLK_GATING_REG0, 27),
+
+ SUNXI_CCU_GATE(A64_CLK_BUS_VE, "bus-ve", "ahb1",
+ BUS_CLK_GATING_REG1, 0),
+ SUNXI_CCU_GATE(A64_CLK_BUS_TCON0, "bus-tcon0", "ahb1",
+ BUS_CLK_GATING_REG1, 3),
+ SUNXI_CCU_GATE(A64_CLK_BUS_TCON1, "bus-tcon1", "ahb1",
+ BUS_CLK_GATING_REG1, 4),
+ SUNXI_CCU_GATE(A64_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1",
+ BUS_CLK_GATING_REG1, 5),
+ SUNXI_CCU_GATE(A64_CLK_BUS_CSI, "bus-csi", "ahb1",
+ BUS_CLK_GATING_REG1, 8),
+ SUNXI_CCU_GATE(A64_CLK_BUS_HDMI, "bus-hdmi", "ahb1",
+ BUS_CLK_GATING_REG1, 10),
+ SUNXI_CCU_GATE(A64_CLK_BUS_DE, "bus-de", "ahb1",
+ BUS_CLK_GATING_REG1, 12),
+ SUNXI_CCU_GATE(A64_CLK_BUS_GPU, "bus-gpu", "ahb1",
+ BUS_CLK_GATING_REG1, 20),
+ SUNXI_CCU_GATE(A64_CLK_BUS_MSGBOX, "bus-msgbox", "ahb1",
+ BUS_CLK_GATING_REG1, 21),
+ SUNXI_CCU_GATE(A64_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1",
+ BUS_CLK_GATING_REG1, 22),
+
+
+ SUNXI_CCU_GATE(A64_CLK_BUS_CODEC, "bus-codec", "apb1",
+ BUS_CLK_GATING_REG3, 0),
+ SUNXI_CCU_GATE(A64_CLK_BUS_SPDIF, "bus-spdif", "apb1",
+ BUS_CLK_GATING_REG3, 1),
+ SUNXI_CCU_GATE(A64_CLK_BUS_PIO, "bus-pio", "apb1",
+ BUS_CLK_GATING_REG3, 5),
+ SUNXI_CCU_GATE(A64_CLK_BUS_THS, "bus-ths", "apb1",
+ BUS_CLK_GATING_REG3, 8),
+ SUNXI_CCU_GATE(A64_CLK_BUS_I2S0, "bus-i2s0", "apb1",
+ BUS_CLK_GATING_REG3, 12),
+ SUNXI_CCU_GATE(A64_CLK_BUS_I2S1, "bus-i2s1", "apb1",
+ BUS_CLK_GATING_REG3, 13),
+ SUNXI_CCU_GATE(A64_CLK_BUS_I2S2, "bus-i2s2", "apb1",
+ BUS_CLK_GATING_REG3, 14),
+
+ SUNXI_CCU_GATE(A64_CLK_BUS_I2C0, "bus-i2c0", "apb2",
+ BUS_CLK_GATING_REG4, 0),
+ SUNXI_CCU_GATE(A64_CLK_BUS_I2C1, "bus-i2c1", "apb2",
+ BUS_CLK_GATING_REG4, 1),
+ SUNXI_CCU_GATE(A64_CLK_BUS_I2C2, "bus-i2c2", "apb2",
+ BUS_CLK_GATING_REG4, 2),
+ SUNXI_CCU_GATE(A64_CLK_BUS_SCR, "bus-scr", "apb2",
+ BUS_CLK_GATING_REG4, 5),
+ SUNXI_CCU_GATE(A64_CLK_BUS_UART0, "bus-uart0", "apb2",
+ BUS_CLK_GATING_REG4, 16),
+ SUNXI_CCU_GATE(A64_CLK_BUS_UART1, "bus-uart1", "apb2",
+ BUS_CLK_GATING_REG4, 17),
+ SUNXI_CCU_GATE(A64_CLK_BUS_UART2, "bus-uart2", "apb2",
+ BUS_CLK_GATING_REG4, 18),
+ SUNXI_CCU_GATE(A64_CLK_BUS_UART3, "bus-uart3", "apb2",
+ BUS_CLK_GATING_REG4, 19),
+ SUNXI_CCU_GATE(A64_CLK_BUS_UART4, "bus-uart4", "apb2",
+ BUS_CLK_GATING_REG4, 20),
+
+ SUNXI_CCU_GATE(A64_CLK_USB_PHY0, "usb-phy0", "hosc",
+ USBPHY_CFG_REG, 8),
+ SUNXI_CCU_GATE(A64_CLK_USB_PHY1, "usb-phy1", "hosc",
+ USBPHY_CFG_REG, 9),
+ SUNXI_CCU_GATE(A64_CLK_USB_HSIC, "usb-hsic", "hosc",
+ USBPHY_CFG_REG, 10),
+ SUNXI_CCU_GATE(A64_CLK_USB_HSIC_12M, "usb-hsic-12m", "hosc",
+ USBPHY_CFG_REG, 11),
+ SUNXI_CCU_GATE(A64_CLK_USB_OHCI0, "usb-ohci0", "hosc",
+ USBPHY_CFG_REG, 16),
+ SUNXI_CCU_GATE(A64_CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0",
+ USBPHY_CFG_REG, 17),
+};
+
+static void
+sun50i_a64_ccu_init(struct sunxi_ccu_softc *sc)
+{
+ uint32_t val;
+
+ /* Set AHB2 source to PLL_PERIPH/2 */
+ val = CCU_READ(sc, AHB2_CFG_REG);
+ val &= ~AHB2_CLK_CFG;
+ val |= __SHIFTIN(AHB2_CLK_CFG_PLL_PERIPH0_2, AHB2_CLK_CFG);
+ CCU_WRITE(sc, AHB2_CFG_REG, val);
+}
+
+static int
+sun50i_a64_ccu_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+sun50i_a64_ccu_attach(device_t parent, device_t self, void *aux)
+{
+ struct sunxi_ccu_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+
+ sc->sc_dev = self;
+ sc->sc_phandle = faa->faa_phandle;
+ sc->sc_bst = faa->faa_bst;
+
+ sc->sc_resets = sun50i_a64_ccu_resets;
+ sc->sc_nresets = __arraycount(sun50i_a64_ccu_resets);
+
+ sc->sc_clks = sun50i_a64_ccu_clks;
+ sc->sc_nclks = __arraycount(sun50i_a64_ccu_clks);
+
+ if (sunxi_ccu_attach(sc) != 0)
+ return;
+
+ aprint_naive("\n");
+ aprint_normal(": A64 CCU\n");
+
+ sun50i_a64_ccu_init(sc);
+
+ sunxi_ccu_print(sc);
+}
Index: src/sys/arch/arm/sunxi/sun50i_a64_ccu.h
diff -u /dev/null src/sys/arch/arm/sunxi/sun50i_a64_ccu.h:1.1
--- /dev/null Thu Sep 7 01:07:04 2017
+++ src/sys/arch/arm/sunxi/sun50i_a64_ccu.h Thu Sep 7 01:07:04 2017
@@ -0,0 +1,200 @@
+/* $NetBSD: sun50i_a64_ccu.h,v 1.1 2017/09/07 01:07:04 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _SUN50I_A64_CCU_H
+#define _SUN50I_A64_CCU_H
+
+#define A64_RST_USB_PHY0 0
+#define A64_RST_USB_PHY1 1
+#define A64_RST_USB_HSIC 2
+#define A64_RST_DRAM 3
+#define A64_RST_MBUS 4
+#define A64_RST_BUS_MIPI_DSI 5
+#define A64_RST_BUS_CE 6
+#define A64_RST_BUS_DMA 7
+#define A64_RST_BUS_MMC0 8
+#define A64_RST_BUS_MMC1 9
+#define A64_RST_BUS_MMC2 10
+#define A64_RST_BUS_NAND 11
+#define A64_RST_BUS_DRAM 12
+#define A64_RST_BUS_EMAC 13
+#define A64_RST_BUS_TS 14
+#define A64_RST_BUS_HSTIMER 15
+#define A64_RST_BUS_SPI0 16
+#define A64_RST_BUS_SPI1 17
+#define A64_RST_BUS_OTG 18
+#define A64_RST_BUS_EHCI0 19
+#define A64_RST_BUS_EHCI1 20
+#define A64_RST_BUS_OHCI0 21
+#define A64_RST_BUS_OHCI1 22
+#define A64_RST_BUS_VE 23
+#define A64_RST_BUS_TCON0 24
+#define A64_RST_BUS_TCON1 25
+#define A64_RST_BUS_DEINTERLACE 26
+#define A64_RST_BUS_CSI 27
+#define A64_RST_BUS_HDMI0 28
+#define A64_RST_BUS_HDMI1 29
+#define A64_RST_BUS_DE 30
+#define A64_RST_BUS_GPU 31
+#define A64_RST_BUS_MSGBOX 32
+#define A64_RST_BUS_SPINLOCK 33
+#define A64_RST_BUS_DBG 34
+#define A64_RST_BUS_LVDS 35
+#define A64_RST_BUS_CODEC 36
+#define A64_RST_BUS_SPDIF 37
+#define A64_RST_BUS_THS 38
+#define A64_RST_BUS_I2S0 39
+#define A64_RST_BUS_I2S1 40
+#define A64_RST_BUS_I2S2 41
+#define A64_RST_BUS_I2C0 42
+#define A64_RST_BUS_I2C1 43
+#define A64_RST_BUS_I2C2 44
+#define A64_RST_BUS_SCR 45
+#define A64_RST_BUS_UART0 46
+#define A64_RST_BUS_UART1 47
+#define A64_RST_BUS_UART2 48
+#define A64_RST_BUS_UART3 49
+#define A64_RST_BUS_UART4 50
+
+#define A64_CLK_OSC_12M 0
+#define A64_CLK_PLL_CPUX 1
+#define A64_CLK_PLL_AUDIO_BASE 2
+#define A64_CLK_PLL_AUDIO 3
+#define A64_CLK_PLL_AUDIO_2X 4
+#define A64_CLK_PLL_AUDIO_4X 5
+#define A64_CLK_PLL_AUDIO_8X 6
+#define A64_CLK_PLL_VIDEO0 7
+#define A64_CLK_PLL_VIDEO0_2X 8
+#define A64_CLK_PLL_VE 9
+#define A64_CLK_PLL_DDR0 10
+#define A64_CLK_PLL_PERIPH0 11
+#define A64_CLK_PLL_PERIPH0_2X 12
+#define A64_CLK_PLL_PERIPH1 13
+#define A64_CLK_PLL_PERIPH1_2X 14
+#define A64_CLK_PLL_VIDEO1 15
+#define A64_CLK_PLL_GPU 16
+#define A64_CLK_PLL_MIPI 17
+#define A64_CLK_PLL_HSIC 18
+#define A64_CLK_PLL_DE 19
+#define A64_CLK_PLL_DDR1 20
+#define A64_CLK_CPUX 21
+#define A64_CLK_AXI 22
+#define A64_CLK_APB 23
+#define A64_CLK_AHB1 24
+#define A64_CLK_APB1 25
+#define A64_CLK_APB2 26
+#define A64_CLK_AHB2 27
+#define A64_CLK_BUS_MIPI_DSI 28
+#define A64_CLK_BUS_CE 29
+#define A64_CLK_BUS_DMA 30
+#define A64_CLK_BUS_MMC0 31
+#define A64_CLK_BUS_MMC1 32
+#define A64_CLK_BUS_MMC2 33
+#define A64_CLK_BUS_NAND 34
+#define A64_CLK_BUS_DRAM 35
+#define A64_CLK_BUS_EMAC 36
+#define A64_CLK_BUS_TS 37
+#define A64_CLK_BUS_HSTIMER 38
+#define A64_CLK_BUS_SPI0 39
+#define A64_CLK_BUS_SPI1 40
+#define A64_CLK_BUS_OTG 41
+#define A64_CLK_BUS_EHCI0 42
+#define A64_CLK_BUS_EHCI1 43
+#define A64_CLK_BUS_OHCI0 44
+#define A64_CLK_BUS_OHCI1 45
+#define A64_CLK_BUS_VE 46
+#define A64_CLK_BUS_TCON0 47
+#define A64_CLK_BUS_TCON1 48
+#define A64_CLK_BUS_DEINTERLACE 49
+#define A64_CLK_BUS_CSI 50
+#define A64_CLK_BUS_HDMI 51
+#define A64_CLK_BUS_DE 52
+#define A64_CLK_BUS_GPU 53
+#define A64_CLK_BUS_MSGBOX 54
+#define A64_CLK_BUS_SPINLOCK 55
+#define A64_CLK_BUS_CODEC 56
+#define A64_CLK_BUS_SPDIF 57
+#define A64_CLK_BUS_PIO 58
+#define A64_CLK_BUS_THS 59
+#define A64_CLK_BUS_I2S0 60
+#define A64_CLK_BUS_I2S1 61
+#define A64_CLK_BUS_I2S2 62
+#define A64_CLK_BUS_I2C0 63
+#define A64_CLK_BUS_I2C1 64
+#define A64_CLK_BUS_I2C2 65
+#define A64_CLK_BUS_SCR 66
+#define A64_CLK_BUS_UART0 67
+#define A64_CLK_BUS_UART1 68
+#define A64_CLK_BUS_UART2 69
+#define A64_CLK_BUS_UART3 70
+#define A64_CLK_BUS_UART4 71
+#define A64_CLK_BUS_DBG 72
+#define A64_CLK_THS 73
+#define A64_CLK_NAND 74
+#define A64_CLK_MMC0 75
+#define A64_CLK_MMC1 76
+#define A64_CLK_MMC2 77
+#define A64_CLK_TS 78
+#define A64_CLK_CE 79
+#define A64_CLK_SPI0 80
+#define A64_CLK_SPI1 81
+#define A64_CLK_I2S0 82
+#define A64_CLK_I2S1 83
+#define A64_CLK_I2S2 84
+#define A64_CLK_SPDIF 85
+#define A64_CLK_USB_PHY0 86
+#define A64_CLK_USB_PHY1 87
+#define A64_CLK_USB_HSIC 88
+#define A64_CLK_USB_HSIC_12M 89
+#define A64_CLK_USB_OHCI0_12M 90
+#define A64_CLK_USB_OHCI0 91
+#define A64_CLK_USB_OHCI1_12M 92
+#define A64_CLK_USB_OHCI1 93
+#define A64_CLK_DRAM 94
+#define A64_CLK_DRAM_VE 95
+#define A64_CLK_DRAM_CSI 96
+#define A64_CLK_DRAM_DEINTERLACE 97
+#define A64_CLK_DRAM_TS 98
+#define A64_CLK_DE 99
+#define A64_CLK_TCON0 100
+#define A64_CLK_TCON1 101
+#define A64_CLK_DEINTERLACE 102
+#define A64_CLK_CSI_MISC 103
+#define A64_CLK_CSI_SCLK 104
+#define A64_CLK_CSI_MCLK 105
+#define A64_CLK_VE 106
+#define A64_CLK_AC_DIG 107
+#define A64_CLK_AC_DIG_4X 108
+#define A64_CLK_AVS 109
+#define A64_CLK_HDMI 110
+#define A64_CLK_HDMI_DDC 111
+#define A64_CLK_MBUS 112
+#define A64_CLK_DSI_DPHY 113
+#define A64_CLK_GPU 114
+
+#endif /* !_SUN50I_A64_CCU_H */
