Module Name: src
Committed By: snj
Date: Sat Sep 23 17:56:31 UTC 2017
Modified Files:
src/sys/arch/powerpc/include [netbsd-8]: fenv.h
Log Message:
Pull up following revision(s) (requested by phx in ticket #291):
sys/arch/powerpc/include/fenv.h: revision 1.4
Fixed feholdexcept() by copying the actual contents of FPSCR to the fenv_t
instead of a double precision floating point representation of it.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.3.6.1 src/sys/arch/powerpc/include/fenv.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/powerpc/include/fenv.h
diff -u src/sys/arch/powerpc/include/fenv.h:1.3 src/sys/arch/powerpc/include/fenv.h:1.3.6.1
--- src/sys/arch/powerpc/include/fenv.h:1.3 Wed Mar 22 23:11:09 2017
+++ src/sys/arch/powerpc/include/fenv.h Sat Sep 23 17:56:31 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: fenv.h,v 1.3 2017/03/22 23:11:09 chs Exp $ */
+/* $NetBSD: fenv.h,v 1.3.6.1 2017/09/23 17:56:31 snj Exp $ */
/*-
* Copyright (c) 2004-2005 David Schultz <[email protected]>
@@ -242,7 +242,7 @@ feholdexcept(fenv_t *__envp)
uint32_t msr;
__mffs(&__r.__d);
- *__envp = __r.__d;
+ *__envp = __r.__bits.__reg;
__r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
__mtfsf(__r.__d);
__updatemsr(__r.__bits.__reg);
