Module Name: src
Committed By: jmcneill
Date: Tue Sep 26 16:12:45 UTC 2017
Modified Files:
src/sys/arch/arm/nvidia: files.tegra tegra210_car.c tegra210_xusbpad.c
tegra_pcie.c tegra_pciereg.h tegra_xusb.c
src/sys/arch/evbarm/conf: TEGRA
Log Message:
More PCIe / XUSBPAD initialization goo for Tegra210.
To generate a diff of this commit:
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/nvidia/files.tegra
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/nvidia/tegra210_car.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/nvidia/tegra210_xusbpad.c
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/nvidia/tegra_pcie.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/nvidia/tegra_pciereg.h
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/nvidia/tegra_xusb.c
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/evbarm/conf/TEGRA
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/nvidia/files.tegra
diff -u src/sys/arch/arm/nvidia/files.tegra:1.44 src/sys/arch/arm/nvidia/files.tegra:1.45
--- src/sys/arch/arm/nvidia/files.tegra:1.44 Fri Sep 22 14:36:22 2017
+++ src/sys/arch/arm/nvidia/files.tegra Tue Sep 26 16:12:45 2017
@@ -1,4 +1,4 @@
-# $NetBSD: files.tegra,v 1.44 2017/09/22 14:36:22 jmcneill Exp $
+# $NetBSD: files.tegra,v 1.45 2017/09/26 16:12:45 jmcneill Exp $
#
# Configuration info for NVIDIA Tegra ARM Peripherals
#
@@ -88,10 +88,13 @@ attach tegra124xpad at fdt with tegra124
file arch/arm/nvidia/tegra124_xusbpad.c tegra124_xusbpad
# XUSB PADCTL (Tegra210)
-device tegra210xpad: tegra_xusbpad
+device tegra210xpad { }: tegra_xusbpad
+device tegra210xphy: tegra210xpad
attach tegra210xpad at fdt with tegra210_xusbpad
+attach tegra210xphy at tegra210xpad
file arch/arm/nvidia/tegra210_xusbpad.c tegra210_xusbpad
+
# UART
attach com at fdt with tegra_com
file arch/arm/nvidia/tegra_com.c tegra_com needs-flag
Index: src/sys/arch/arm/nvidia/tegra210_car.c
diff -u src/sys/arch/arm/nvidia/tegra210_car.c:1.13 src/sys/arch/arm/nvidia/tegra210_car.c:1.14
--- src/sys/arch/arm/nvidia/tegra210_car.c:1.13 Mon Sep 25 08:55:07 2017
+++ src/sys/arch/arm/nvidia/tegra210_car.c Tue Sep 26 16:12:45 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_car.c,v 1.13 2017/09/25 08:55:07 jmcneill Exp $ */
+/* $NetBSD: tegra210_car.c,v 1.14 2017/09/26 16:12:45 jmcneill Exp $ */
/*-
* Copyright (c) 2015-2017 Jared McNeill <jmcne...@invisible.ca>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.13 2017/09/25 08:55:07 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.14 2017/09/26 16:12:45 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -609,6 +609,9 @@ struct tegra210_init_parent {
{ "XUSB_FS_SRC", "PLL_U_48M", 48000000, 0 },
{ "PLL_U_OUT1", NULL, 48000000, 1 },
{ "PLL_U_OUT2", NULL, 60000000, 1 },
+ { "CML0", NULL, 0, 1 },
+ { "AFI", NULL, 0, 1 },
+ { "PCIE", NULL, 0, 1 },
};
struct tegra210_car_rst {
@@ -817,9 +820,15 @@ tegra210_car_utmip_init(struct tegra210_
tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
0x3, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT);
+ bus_space_write_4(bst, bsh, CAR_CLK_ENB_U_SET_REG, CAR_DEV_U_AFI);
+ bus_space_write_4(bst, bsh, CAR_CLK_ENB_U_SET_REG, CAR_DEV_U_PCIE);
+
bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, CAR_DEV_L_USBD);
bus_space_write_4(bst, bsh, CAR_RST_DEV_H_CLR_REG, CAR_DEV_H_USB2);
bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_XUSB);
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_AFI);
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_PCIE);
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_PCIEXCLK);
bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_PEX_USB_UPHY);
bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_SATA_USB_UPHY);
Index: src/sys/arch/arm/nvidia/tegra210_xusbpad.c
diff -u src/sys/arch/arm/nvidia/tegra210_xusbpad.c:1.7 src/sys/arch/arm/nvidia/tegra210_xusbpad.c:1.8
--- src/sys/arch/arm/nvidia/tegra210_xusbpad.c:1.7 Mon Sep 25 00:03:34 2017
+++ src/sys/arch/arm/nvidia/tegra210_xusbpad.c Tue Sep 26 16:12:45 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_xusbpad.c,v 1.7 2017/09/25 00:03:34 jmcneill Exp $ */
+/* $NetBSD: tegra210_xusbpad.c,v 1.8 2017/09/26 16:12:45 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_xusbpad.c,v 1.7 2017/09/25 00:03:34 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_xusbpad.c,v 1.8 2017/09/26 16:12:45 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -158,6 +158,17 @@ struct tegra210_xusbpad_softc {
bool sc_enabled;
};
+struct tegra210_xusbpad_phy_softc {
+ device_t sc_dev;
+ int sc_phandle;
+ struct tegra210_xusbpad_softc *sc_xusbpad;
+};
+
+struct tegra210_xusbpad_phy_attach_args {
+ struct tegra210_xusbpad_softc *paa_xusbpad;
+ int paa_phandle;
+};
+
#define RD4(sc, reg) \
bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
#define WR4(sc, reg, val) \
@@ -550,16 +561,18 @@ tegra210_xusbpad_configure_pads(struct t
}
}
- /* Configure lanes */
+ /* Attach PHYs */
phandle = of_find_firstchild_byname(phandle, "lanes");
if (phandle == -1) {
aprint_error_dev(sc->sc_dev, "no 'pads/%s/lanes' node\n", name);
return;
}
for (child = OF_child(phandle); child; child = OF_peer(child)) {
- if (!fdtbus_status_okay(child))
- continue;
- tegra210_xusbpad_configure_lane(sc, child);
+ struct tegra210_xusbpad_phy_attach_args paa = {
+ .paa_xusbpad = sc,
+ .paa_phandle = child
+ };
+ config_found(sc->sc_dev, &paa, NULL);
}
}
@@ -813,5 +826,70 @@ tegra210_xusbpad_attach(device_t parent,
tegra210_xusbpad_configure_ports(sc);
}
+static void *
+tegra210_xusbpad_phy_acquire(device_t dev, const void *data, size_t len)
+{
+ struct tegra210_xusbpad_phy_softc * const sc = device_private(dev);
+
+ if (len != 0)
+ return NULL;
+
+ return sc;
+}
+
+static void
+tegra210_xusbpad_phy_release(device_t dev, void *priv)
+{
+};
+
+static int
+tegra210_xusbpad_phy_enable(device_t dev, void *priv, bool enable)
+{
+ struct tegra210_xusbpad_phy_softc * const sc = device_private(dev);
+
+ if (enable == false)
+ return ENXIO; /* not implemented */
+
+ tegra210_xusbpad_configure_lane(sc->sc_xusbpad, sc->sc_phandle);
+
+ return 0;
+}
+
+static const struct fdtbus_phy_controller_func tegra210_xusbpad_phy_funcs = {
+ .acquire = tegra210_xusbpad_phy_acquire,
+ .release = tegra210_xusbpad_phy_release,
+ .enable = tegra210_xusbpad_phy_enable,
+};
+
CFATTACH_DECL_NEW(tegra210_xusbpad, sizeof(struct tegra210_xusbpad_softc),
tegra210_xusbpad_match, tegra210_xusbpad_attach, NULL, NULL);
+
+static int
+tegra210_xusbpad_phy_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct tegra210_xusbpad_phy_attach_args * const paa = aux;
+
+ if (!fdtbus_status_okay(paa->paa_phandle))
+ return 0;
+
+ return 1;
+}
+
+static void
+tegra210_xusbpad_phy_attach(device_t parent, device_t self, void *aux)
+{
+ struct tegra210_xusbpad_phy_softc * const sc = device_private(self);
+ struct tegra210_xusbpad_phy_attach_args * const paa = aux;
+
+ sc->sc_dev = self;
+ sc->sc_phandle = paa->paa_phandle;
+ sc->sc_xusbpad = paa->paa_xusbpad;
+
+ aprint_naive("\n");
+ aprint_normal(": %s\n", fdtbus_get_string(sc->sc_phandle, "name"));
+
+ fdtbus_register_phy_controller(self, sc->sc_phandle, &tegra210_xusbpad_phy_funcs);
+}
+
+CFATTACH_DECL_NEW(tegra210xphy, sizeof(struct tegra210_xusbpad_phy_softc),
+ tegra210_xusbpad_phy_match, tegra210_xusbpad_phy_attach, NULL, NULL);
Index: src/sys/arch/arm/nvidia/tegra_pcie.c
diff -u src/sys/arch/arm/nvidia/tegra_pcie.c:1.20 src/sys/arch/arm/nvidia/tegra_pcie.c:1.21
--- src/sys/arch/arm/nvidia/tegra_pcie.c:1.20 Mon Sep 25 08:55:27 2017
+++ src/sys/arch/arm/nvidia/tegra_pcie.c Tue Sep 26 16:12:45 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_pcie.c,v 1.20 2017/09/25 08:55:27 jmcneill Exp $ */
+/* $NetBSD: tegra_pcie.c,v 1.21 2017/09/26 16:12:45 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.20 2017/09/25 08:55:27 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.21 2017/09/26 16:12:45 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -48,6 +48,7 @@ __KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c
#include <arm/nvidia/tegra_reg.h>
#include <arm/nvidia/tegra_pciereg.h>
+#include <arm/nvidia/tegra_pmcreg.h>
#include <arm/nvidia/tegra_var.h>
#include <dev/fdt/fdtvar.h>
@@ -74,6 +75,7 @@ struct tegra_pcie_softc {
bus_dma_tag_t sc_dmat;
bus_space_tag_t sc_bst;
bus_space_handle_t sc_bsh_afi;
+ bus_space_handle_t sc_bsh_pads;
bus_space_handle_t sc_bsh_rpconf;
int sc_phandle;
@@ -92,6 +94,7 @@ struct tegra_pcie_softc {
static int tegra_pcie_intr(void *);
static void tegra_pcie_init(pci_chipset_tag_t, void *);
static void tegra_pcie_enable(struct tegra_pcie_softc *);
+static void tegra_pcie_enable_ports(struct tegra_pcie_softc *);
static void tegra_pcie_enable_clocks(struct tegra_pcie_softc *);
static void tegra_pcie_setup(struct tegra_pcie_softc * const);
static void tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const,
@@ -143,15 +146,19 @@ tegra_pcie_attach(device_t parent, devic
struct fdt_attach_args * const faa = aux;
struct extent *ioext, *memext, *pmemext;
struct pcibus_attach_args pba;
- bus_addr_t afi_addr, cs_addr;
- bus_size_t afi_size, cs_size;
+ bus_addr_t afi_addr, cs_addr, pads_addr;
+ bus_size_t afi_size, cs_size, pads_size;
char intrstr[128];
int error;
- if (fdtbus_get_reg(faa->faa_phandle, 1, &afi_addr, &afi_size) != 0) {
+ if (fdtbus_get_reg_byname(faa->faa_phandle, "afi", &afi_addr, &afi_size) != 0) {
aprint_error(": couldn't get afi registers\n");
return;
}
+ if (fdtbus_get_reg_byname(faa->faa_phandle, "pads", &pads_addr, &pads_size) != 0) {
+ aprint_error(": couldn't get pads registers\n");
+ return;
+ }
#if notyet
if (fdtbus_get_reg(faa->faa_phandle, 2, &cs_addr, &cs_size) != 0) {
aprint_error(": couldn't get cs registers\n");
@@ -172,6 +179,12 @@ tegra_pcie_attach(device_t parent, devic
aprint_error(": couldn't map afi registers: %d\n", error);
return;
}
+ error = bus_space_map(sc->sc_bst, pads_addr, pads_size, 0,
+ &sc->sc_bsh_pads);
+ if (error) {
+ aprint_error(": couldn't map afi registers: %d\n", error);
+ return;
+ }
error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0,
&sc->sc_bsh_rpconf);
if (error) {
@@ -187,6 +200,9 @@ tegra_pcie_attach(device_t parent, devic
aprint_naive("\n");
aprint_normal(": PCIE\n");
+ tegra_pmc_power(PMC_PARTID_PCX, true);
+ tegra_pmc_remove_clamping(PMC_PARTID_PCX);
+
tegra_pcie_enable_clocks(sc);
if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
@@ -232,6 +248,8 @@ tegra_pcie_attach(device_t parent, devic
tegra_pcie_enable(sc);
+ tegra_pcie_enable_ports(sc);
+
memset(&pba, 0, sizeof(pba));
pba.pba_flags = PCI_FLAGS_MRL_OKAY |
PCI_FLAGS_MRM_OKAY |
@@ -338,10 +356,108 @@ tegra_pcie_enable_clocks(struct tegra_pc
}
static void
+tegra_pcie_reset_port(struct tegra_pcie_softc * const sc, int index)
+{
+ uint32_t val;
+
+ val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index));
+ val &= ~AFI_PEXn_CTRL_RST_L;
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val);
+
+ delay(2000);
+
+ val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index));
+ val |= AFI_PEXn_CTRL_RST_L;
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val);
+}
+
+static void
+tegra_pcie_enable_ports(struct tegra_pcie_softc * const sc)
+{
+ const u_int *data;
+ int child, len;
+ uint32_t val;
+
+ for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) {
+ if (!fdtbus_status_okay(child))
+ continue;
+ data = fdtbus_get_prop(child, "reg", &len);
+ if (data == NULL || len < 4)
+ continue;
+ const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1;
+
+ val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index));
+ val |= AFI_PEXn_CTRL_CLKREQ_EN;
+ val |= AFI_PEXn_CTRL_REFCLK_EN;
+ val |= AFI_PEXn_CTRL_REFCLK_OVERRIDE_EN;
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val);
+
+ tegra_pcie_reset_port(sc, index);
+ }
+}
+
+static void
tegra_pcie_setup(struct tegra_pcie_softc * const sc)
{
+ uint32_t val, cfg, lanes;
+ int child, len;
+ const u_int *data;
size_t i;
+ /* Enable PLLE control */
+ val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG);
+ val &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
+ val |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG, val);
+
+ /* Disable PEX clock bias pad power down */
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXBIAS_CTRL_REG, 0);
+
+ /* Configure PCIE mode and enable ports */
+ cfg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG);
+ cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(0);
+ cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(1);
+ cfg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG;
+
+ lanes = 0;
+ for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) {
+ if (!fdtbus_status_okay(child))
+ continue;
+ data = fdtbus_get_prop(child, "reg", &len);
+ if (data == NULL || len < 4)
+ continue;
+ const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1;
+ if (of_getprop_uint32(child, "nvidia,num-lanes", &val) != 0)
+ continue;
+ lanes |= (val << (index << 3));
+ cfg &= ~AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(index);
+ }
+
+ switch (lanes) {
+ case 0x0104:
+ aprint_normal_dev(sc->sc_dev, "lane config: x4 x1\n");
+ cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_4_1,
+ AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG);
+ break;
+ case 0x0102:
+ aprint_normal_dev(sc->sc_dev, "lane config: x2 x1\n");
+ cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_2_1,
+ AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG);
+ break;
+ }
+
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG, cfg);
+
+ /* Configure refclk pad */
+ const char * const tegra124_compat[] = { "nvidia,tegra124-pcie", NULL };
+ if (of_match_compatible(sc->sc_phandle, tegra124_compat))
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, PADS_REFCLK_CFG0_REG,
+ 0x44ac44ac);
+ const char * const tegra210_compat[] = { "nvidia,tegra210-pcie", NULL };
+ if (of_match_compatible(sc->sc_phandle, tegra210_compat))
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, PADS_REFCLK_CFG0_REG,
+ 0x90b890b8);
+
/*
* Map PCI address spaces into ARM address space via
* HyperTransport-like "FPCI".
Index: src/sys/arch/arm/nvidia/tegra_pciereg.h
diff -u src/sys/arch/arm/nvidia/tegra_pciereg.h:1.3 src/sys/arch/arm/nvidia/tegra_pciereg.h:1.4
--- src/sys/arch/arm/nvidia/tegra_pciereg.h:1.3 Sat Nov 14 01:38:58 2015
+++ src/sys/arch/arm/nvidia/tegra_pciereg.h Tue Sep 26 16:12:45 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_pciereg.h,v 1.3 2015/11/14 01:38:58 jakllsch Exp $ */
+/* $NetBSD: tegra_pciereg.h,v 1.4 2017/09/26 16:12:45 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -29,6 +29,9 @@
#ifndef _ARM_TEGRA_PCIEREG_H
#define _ARM_TEGRA_PCIEREG_H
+/* PADS */
+#define PADS_REFCLK_CFG0_REG 0xc8
+
/* AFI */
#define AFI_AXI_NBAR 9
@@ -52,6 +55,11 @@
#define AFI_INTR_SIGNATURE_REG 0xbc
#define AFI_SM_INTR_ENABLE_REG 0xc4
#define AFI_AFI_INTR_ENABLE_REG 0xc8
+#define AFI_PCIE_CONFIG_REG 0xf8
+#define AFI_PEXn_CTRL_REG(n) (0x110 + (n) * 8)
+#define AFI_PEXn_STATUS_REG(n) (0x114 + (n) * 8)
+#define AFI_PLLE_CONTROL_REG 0x160
+#define AFI_PEXBIAS_CTRL_REG 0x168
#define AFI_MSG_REG 0x190
#define AFI_INTR_MASK_MSI __BIT(8)
@@ -60,6 +68,21 @@
#define AFI_INTR_CODE_INT_CODE __BITS(4,0)
#define AFI_INTR_CODE_SM_MSG 6
+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG __BITS(23,20)
+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_2_1 0
+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_4_1 1
+#define AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(n) __BIT(1 + (n))
+
+#define AFI_PEXn_CTRL_REFCLK_OVERRIDE_EN __BIT(4)
+#define AFI_PEXn_CTRL_REFCLK_EN __BIT(3)
+#define AFI_PEXn_CTRL_CLKREQ_EN __BIT(1)
+#define AFI_PEXn_CTRL_RST_L __BIT(0)
+
+#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL __BIT(9)
+#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN __BIT(1)
+
+#define AFI_PEXBIAS_CTRL_PWRD __BIT(0)
+
#define AFI_MSG_INT1 __BITS(27,24)
#define AFI_MSG_PM_PME1 __BIT(20)
#define AFI_MSG_INT0 __BITS(11,8)
Index: src/sys/arch/arm/nvidia/tegra_xusb.c
diff -u src/sys/arch/arm/nvidia/tegra_xusb.c:1.11 src/sys/arch/arm/nvidia/tegra_xusb.c:1.12
--- src/sys/arch/arm/nvidia/tegra_xusb.c:1.11 Mon Sep 25 00:03:34 2017
+++ src/sys/arch/arm/nvidia/tegra_xusb.c Tue Sep 26 16:12:45 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_xusb.c,v 1.11 2017/09/25 00:03:34 jmcneill Exp $ */
+/* $NetBSD: tegra_xusb.c,v 1.12 2017/09/26 16:12:45 jmcneill Exp $ */
/*
* Copyright (c) 2016 Jonathan A. Kollasch
@@ -30,7 +30,7 @@
#include "opt_tegra.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.11 2017/09/25 00:03:34 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.12 2017/09/26 16:12:45 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -159,9 +159,10 @@ tegra_xusb_attach(device_t parent, devic
bus_addr_t addr;
bus_size_t size;
struct fdtbus_reset *rst;
+ struct fdtbus_phy *phy;
struct clk *clk;
uint32_t rate;
- int error;
+ int error, n;
aprint_naive("\n");
aprint_normal(": XUSB\n");
@@ -244,10 +245,17 @@ tegra_xusb_attach(device_t parent, devic
}
aprint_normal_dev(self, "interrupting on %s\n", intrstr);
+ /* Enable PHYs */
+ for (n = 0; (phy = fdtbus_phy_get_index(faa->faa_phandle, n)) != NULL; n++)
+ if (fdtbus_phy_enable(phy, true) != 0)
+ aprint_error_dev(self, "failed to enable PHY #%d\n", n);
+
/* Enable XUSB power rails */
tegra_pmc_power(PMC_PARTID_XUSBC, true); /* Host/USB2.0 */
+ tegra_pmc_remove_clamping(PMC_PARTID_XUSBC);
tegra_pmc_power(PMC_PARTID_XUSBA, true); /* SuperSpeed */
+ tegra_pmc_remove_clamping(PMC_PARTID_XUSBA);
/* Enable XUSB clocks */
Index: src/sys/arch/evbarm/conf/TEGRA
diff -u src/sys/arch/evbarm/conf/TEGRA:1.32 src/sys/arch/evbarm/conf/TEGRA:1.33
--- src/sys/arch/evbarm/conf/TEGRA:1.32 Sat Sep 23 23:54:54 2017
+++ src/sys/arch/evbarm/conf/TEGRA Tue Sep 26 16:12:45 2017
@@ -1,5 +1,5 @@
#
-# $NetBSD: TEGRA,v 1.32 2017/09/23 23:54:54 jmcneill Exp $
+# $NetBSD: TEGRA,v 1.33 2017/09/26 16:12:45 jmcneill Exp $
#
# NVIDIA Tegra family SoCs
#
@@ -96,6 +96,7 @@ tegrapinmux* at fdt? # MPIO
# XUSB PADCTL
tegra124xpad* at fdt? # XUSB PADCTL (T124)
tegra210xpad* at fdt? # XUSB PADCTL (T210)
+tegra210xphy* at tegra210xpad?
# PCIE
tegrapcie0 at fdt? # PCIE
