Module Name: src
Committed By: msaitoh
Date: Fri Oct 13 13:53:54 UTC 2017
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add the following instruction bits in Structured Extended Flags Enumeration
Leaf from "Intel Architecture Instruction Set Extensions and Future Features
Programming Reference" (319433-030):
AVX512_IFMA
AVX512_VBMI
AVX512_VBMI2
GFNI
VAES
VPCLMULQDQ
AVX512_VNNI
AVX512_BITALG
AVX512_VPOPCNTDQ
AVX512_4VNNIW
AVX512_4FMAPS
To generate a diff of this commit:
cvs rdiff -u -r1.102 -r1.103 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.102 src/sys/arch/x86/include/specialreg.h:1.103
--- src/sys/arch/x86/include/specialreg.h:1.102 Thu Sep 7 06:40:42 2017
+++ src/sys/arch/x86/include/specialreg.h Fri Oct 13 13:53:54 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.102 2017/09/07 06:40:42 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.103 2017/10/13 13:53:54 msaitoh Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -345,6 +345,7 @@
#define CPUID_SEF_RDSEED __BIT(18)
#define CPUID_SEF_ADX __BIT(19)
#define CPUID_SEF_SMAP __BIT(20)
+#define CPUID_SEF_AVX512_IFMA __BIT(21)
#define CPUID_SEF_CLFLUSHOPT __BIT(23)
#define CPUID_SEF_CLWB __BIT(24)
#define CPUID_SEF_PT __BIT(25)
@@ -361,24 +362,41 @@
"\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \
"\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \
"\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \
- "\25" "SMAP" "\30" "CLFLUSHOPT" \
+ "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \
"\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \
"\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL"
/* %ecx */
#define CPUID_SEF_PREFETCHWT1 __BIT(0)
+#define CPUID_SEF_AVX512_VBMI __BIT(1)
#define CPUID_SEF_UMIP __BIT(2)
#define CPUID_SEF_PKU __BIT(3)
#define CPUID_SEF_OSPKE __BIT(4)
+#define CPUID_SEF_AVX512_VBMI2 __BIT(6)
+#define CPUID_SEF_GFNI __BIT(8)
+#define CPUID_SEF_VAES __BIT(9)
+#define CPUID_SEF_VPCLMULQDQ __BIT(10)
+#define CPUID_SEF_AVX512_VNNI __BIT(11)
+#define CPUID_SEF_AVX512_BITALG __BIT(12)
+#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14)
#define CPUID_SEF_RDPID __BIT(22)
#define CPUID_SEF_SGXLC __BIT(30)
#define CPUID_SEF_FLAGS1 "\20" \
- "\1" "PREFETCHWT1" "\3" "UMIP" "\4" "PKU" \
- "\5" "OSPKE" \
+ "\1" "PREFETCHWT1" "\2" "AVX512_VBMI" "\3" "UMIP" "\4" "PKU" \
+ "\5" "OSPKE" "\7" "AVX512_VBMI2" \
+ "\11" "GFNI" "\12" "VAES" "\13" "VPCLMULQDQ" "\14" "AVX512_VNNI"\
+ "\15" "AVX512_BITALG" "\17" "AVX512_VPOPCNTDQ" \
"\27" "RDPID" \
"\37" "SGXLC"
+/* %edx */
+#define CPUID_SEF_AVX512_4VNNIW __BIT(2)
+#define CPUID_SEF_AVX512_4FMAPS __BIT(3)
+
+#define CPUID_SEF_FLAGS2 "\20" \
+ "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS"
+
/*
* CPUID Processor extended state Enumeration Fn0000000d
*
