Module Name: src Committed By: jmcneill Date: Sat Oct 28 12:07:40 UTC 2017
Modified Files: src/sys/arch/arm/sunxi: sun8i_a83t_ccu.c sun8i_a83t_ccu.h Log Message: Add A83T clock IDs. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/sunxi/sun8i_a83t_ccu.c \ src/sys/arch/arm/sunxi/sun8i_a83t_ccu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/arm/sunxi/sun8i_a83t_ccu.c diff -u src/sys/arch/arm/sunxi/sun8i_a83t_ccu.c:1.1 src/sys/arch/arm/sunxi/sun8i_a83t_ccu.c:1.2 --- src/sys/arch/arm/sunxi/sun8i_a83t_ccu.c:1.1 Thu Jul 6 22:10:14 2017 +++ src/sys/arch/arm/sunxi/sun8i_a83t_ccu.c Sat Oct 28 12:07:40 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: sun8i_a83t_ccu.c,v 1.1 2017/07/06 22:10:14 jmcneill Exp $ */ +/* $NetBSD: sun8i_a83t_ccu.c,v 1.2 2017/10/28 12:07:40 jmcneill Exp $ */ /*- * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca> @@ -29,7 +29,7 @@ #include <sys/cdefs.h> -__KERNEL_RCSID(1, "$NetBSD: sun8i_a83t_ccu.c,v 1.1 2017/07/06 22:10:14 jmcneill Exp $"); +__KERNEL_RCSID(1, "$NetBSD: sun8i_a83t_ccu.c,v 1.2 2017/10/28 12:07:40 jmcneill Exp $"); #include <sys/param.h> #include <sys/bus.h> @@ -41,7 +41,7 @@ __KERNEL_RCSID(1, "$NetBSD: sun8i_a83t_c #include <arm/sunxi/sunxi_ccu.h> #include <arm/sunxi/sun8i_a83t_ccu.h> -#define PLL_PERIPH0_CTRL_REG 0x028 +#define PLL_PERIPH_CTRL_REG 0x028 #define AHB1_APB1_CFG_REG 0x054 #define APB2_CFG_REG 0x058 #define BUS_CLK_GATING_REG0 0x060 @@ -70,66 +70,49 @@ CFATTACH_DECL_NEW(sunxi_a83t_ccu, sizeof sun8i_a83t_ccu_match, sun8i_a83t_ccu_attach, NULL, NULL); static struct sunxi_ccu_reset sun8i_a83t_ccu_resets[] = { - SUNXI_CCU_RESET(H3_RST_USB_PHY0, USBPHY_CFG_REG, 0), - SUNXI_CCU_RESET(H3_RST_USB_PHY1, USBPHY_CFG_REG, 1), - SUNXI_CCU_RESET(H3_RST_USB_PHY2, USBPHY_CFG_REG, 2), - SUNXI_CCU_RESET(H3_RST_USB_PHY3, USBPHY_CFG_REG, 3), - - SUNXI_CCU_RESET(H3_RST_MBUS, MBUS_RST_REG, 31), - - SUNXI_CCU_RESET(H3_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), - SUNXI_CCU_RESET(H3_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), - SUNXI_CCU_RESET(H3_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), - SUNXI_CCU_RESET(H3_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), - SUNXI_CCU_RESET(H3_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), - SUNXI_CCU_RESET(H3_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), - SUNXI_CCU_RESET(H3_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), - SUNXI_CCU_RESET(H3_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), - SUNXI_CCU_RESET(H3_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), - SUNXI_CCU_RESET(H3_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), - SUNXI_CCU_RESET(H3_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), - SUNXI_CCU_RESET(H3_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), - SUNXI_CCU_RESET(H3_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), - SUNXI_CCU_RESET(H3_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), - SUNXI_CCU_RESET(H3_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), - SUNXI_CCU_RESET(H3_RST_BUS_EHCI2, BUS_SOFT_RST_REG0, 26), - SUNXI_CCU_RESET(H3_RST_BUS_EHCI3, BUS_SOFT_RST_REG0, 27), - SUNXI_CCU_RESET(H3_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), - SUNXI_CCU_RESET(H3_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), - SUNXI_CCU_RESET(H3_RST_BUS_OHCI2, BUS_SOFT_RST_REG0, 30), - SUNXI_CCU_RESET(H3_RST_BUS_OHCI3, BUS_SOFT_RST_REG0, 31), + SUNXI_CCU_RESET(A83T_RST_USB_PHY0, USBPHY_CFG_REG, 0), + SUNXI_CCU_RESET(A83T_RST_USB_PHY1, USBPHY_CFG_REG, 1), + + SUNXI_CCU_RESET(A83T_RST_MBUS, MBUS_RST_REG, 31), + + SUNXI_CCU_RESET(A83T_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), + SUNXI_CCU_RESET(A83T_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), + SUNXI_CCU_RESET(A83T_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), + SUNXI_CCU_RESET(A83T_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), + SUNXI_CCU_RESET(A83T_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), + SUNXI_CCU_RESET(A83T_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), + SUNXI_CCU_RESET(A83T_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), + SUNXI_CCU_RESET(A83T_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), + SUNXI_CCU_RESET(A83T_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), + SUNXI_CCU_RESET(A83T_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), + SUNXI_CCU_RESET(A83T_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), + SUNXI_CCU_RESET(A83T_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), + SUNXI_CCU_RESET(A83T_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), + SUNXI_CCU_RESET(A83T_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), - SUNXI_CCU_RESET(H3_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), - SUNXI_CCU_RESET(H3_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), - SUNXI_CCU_RESET(H3_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), - SUNXI_CCU_RESET(H3_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), - SUNXI_CCU_RESET(H3_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), - SUNXI_CCU_RESET(H3_RST_BUS_TVE, BUS_SOFT_RST_REG1, 9), - SUNXI_CCU_RESET(H3_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), - SUNXI_CCU_RESET(H3_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), - SUNXI_CCU_RESET(H3_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), - SUNXI_CCU_RESET(H3_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), - SUNXI_CCU_RESET(H3_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), - SUNXI_CCU_RESET(H3_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), - SUNXI_CCU_RESET(H3_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), - - SUNXI_CCU_RESET(H3_RST_BUS_EPHY, BUS_SOFT_RST_REG2, 2), - - SUNXI_CCU_RESET(H3_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), - SUNXI_CCU_RESET(H3_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), - SUNXI_CCU_RESET(H3_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), - SUNXI_CCU_RESET(H3_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), - SUNXI_CCU_RESET(H3_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), - SUNXI_CCU_RESET(H3_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), - - SUNXI_CCU_RESET(H3_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), - SUNXI_CCU_RESET(H3_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), - SUNXI_CCU_RESET(H3_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), - SUNXI_CCU_RESET(H3_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), - SUNXI_CCU_RESET(H3_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), - SUNXI_CCU_RESET(H3_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), - SUNXI_CCU_RESET(H3_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), - SUNXI_CCU_RESET(H3_RST_BUS_SCR, BUS_SOFT_RST_REG4, 20), + SUNXI_CCU_RESET(A83T_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), + SUNXI_CCU_RESET(A83T_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), + SUNXI_CCU_RESET(A83T_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), + SUNXI_CCU_RESET(A83T_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), + SUNXI_CCU_RESET(A83T_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), + SUNXI_CCU_RESET(A83T_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), + SUNXI_CCU_RESET(A83T_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), + SUNXI_CCU_RESET(A83T_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), + SUNXI_CCU_RESET(A83T_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), + SUNXI_CCU_RESET(A83T_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), + + SUNXI_CCU_RESET(A83T_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), + SUNXI_CCU_RESET(A83T_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), + SUNXI_CCU_RESET(A83T_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), + SUNXI_CCU_RESET(A83T_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), + + SUNXI_CCU_RESET(A83T_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), + SUNXI_CCU_RESET(A83T_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), + SUNXI_CCU_RESET(A83T_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), + SUNXI_CCU_RESET(A83T_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), + SUNXI_CCU_RESET(A83T_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), + SUNXI_CCU_RESET(A83T_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), + SUNXI_CCU_RESET(A83T_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), }; static const char *ahb1_parents[] = { "losc", "hosc", "pll_periph" }; @@ -139,8 +122,8 @@ static const char *apb2_parents[] = { "l static const char *mod_parents[] = { "hosc", "pll_periph" }; static struct sunxi_ccu_clk sun8i_a83t_ccu_clks[] = { - SUNXI_CCU_NKMP(H3_CLK_PLL_PERIPH0, "pll_periph", "hosc", - PLL_PERIPH0_CTRL_REG, /* reg */ + SUNXI_CCU_NKMP(A83T_CLK_PLL_PERIPH, "pll_periph", "hosc", + PLL_PERIPH_CTRL_REG, /* reg */ __BITS(15,8), /* n */ 0, /* k */ __BIT(18), /* m */ @@ -148,7 +131,7 @@ static struct sunxi_ccu_clk sun8i_a83t_c __BIT(31), /* enable */ SUNXI_CCU_NKMP_FACTOR_N_EXACT), - SUNXI_CCU_PREDIV(H3_CLK_AHB1, "ahb1", ahb1_parents, + SUNXI_CCU_PREDIV(A83T_CLK_AHB1, "ahb1", ahb1_parents, AHB1_APB1_CFG_REG, /* reg */ __BITS(7,6), /* prediv */ __BIT(3), /* prediv_sel */ @@ -156,7 +139,7 @@ static struct sunxi_ccu_clk sun8i_a83t_c __BITS(13,12), /* sel */ SUNXI_CCU_PREDIV_POWER_OF_TWO), - SUNXI_CCU_PREDIV(H3_CLK_AHB2, "ahb2", ahb2_parents, + SUNXI_CCU_PREDIV(A83T_CLK_AHB2, "ahb2", ahb2_parents, APB2_CFG_REG, /* reg */ 0, /* prediv */ __BIT(1), /* prediv_sel */ @@ -164,13 +147,13 @@ static struct sunxi_ccu_clk sun8i_a83t_c __BITS(1,0), /* sel */ SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), - SUNXI_CCU_DIV(H3_CLK_APB1, "apb1", apb1_parents, + SUNXI_CCU_DIV(A83T_CLK_APB1, "apb1", apb1_parents, AHB1_APB1_CFG_REG, /* reg */ __BITS(9,8), /* div */ 0, /* sel */ SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), - SUNXI_CCU_NM(H3_CLK_APB2, "apb2", apb2_parents, + SUNXI_CCU_NM(A83T_CLK_APB2, "apb2", apb2_parents, APB2_CFG_REG, /* reg */ __BITS(17,16), /* n */ __BITS(4,0), /* m */ @@ -178,77 +161,57 @@ static struct sunxi_ccu_clk sun8i_a83t_c 0, /* enable */ SUNXI_CCU_NM_POWER_OF_TWO), - SUNXI_CCU_NM(H3_CLK_MMC0, "mmc0", mod_parents, + SUNXI_CCU_NM(A83T_CLK_MMC0, "mmc0", mod_parents, SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), - SUNXI_CCU_NM(H3_CLK_MMC1, "mmc1", mod_parents, + SUNXI_CCU_NM(A83T_CLK_MMC1, "mmc1", mod_parents, SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), - SUNXI_CCU_NM(H3_CLK_MMC2, "mmc2", mod_parents, + SUNXI_CCU_NM(A83T_CLK_MMC2, "mmc2", mod_parents, SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), - SUNXI_CCU_GATE(H3_CLK_BUS_MMC0, "bus-mmc0", "ahb1", + SUNXI_CCU_GATE(A83T_CLK_BUS_MMC0, "bus-mmc0", "ahb1", BUS_CLK_GATING_REG0, 8), - SUNXI_CCU_GATE(H3_CLK_BUS_MMC1, "bus-mmc1", "ahb1", + SUNXI_CCU_GATE(A83T_CLK_BUS_MMC1, "bus-mmc1", "ahb1", BUS_CLK_GATING_REG0, 9), - SUNXI_CCU_GATE(H3_CLK_BUS_MMC2, "bus-mmc2", "ahb1", + SUNXI_CCU_GATE(A83T_CLK_BUS_MMC2, "bus-mmc2", "ahb1", BUS_CLK_GATING_REG0, 10), - SUNXI_CCU_GATE(H3_CLK_BUS_EMAC, "bus-emac", "ahb2", + SUNXI_CCU_GATE(A83T_CLK_BUS_EMAC, "bus-emac", "ahb2", BUS_CLK_GATING_REG0, 17), - SUNXI_CCU_GATE(H3_CLK_BUS_OTG, "bus-otg", "ahb1", + SUNXI_CCU_GATE(A83T_CLK_BUS_OTG, "bus-otg", "ahb1", BUS_CLK_GATING_REG0, 23), - SUNXI_CCU_GATE(H3_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", + SUNXI_CCU_GATE(A83T_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", BUS_CLK_GATING_REG0, 24), - SUNXI_CCU_GATE(H3_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", + SUNXI_CCU_GATE(A83T_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", BUS_CLK_GATING_REG0, 25), - SUNXI_CCU_GATE(H3_CLK_BUS_EHCI2, "bus-ehci2", "ahb2", - BUS_CLK_GATING_REG0, 26), - SUNXI_CCU_GATE(H3_CLK_BUS_EHCI3, "bus-ehci3", "ahb2", - BUS_CLK_GATING_REG0, 27), - SUNXI_CCU_GATE(H3_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", + SUNXI_CCU_GATE(A83T_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", BUS_CLK_GATING_REG0, 28), - SUNXI_CCU_GATE(H3_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", - BUS_CLK_GATING_REG0, 29), - SUNXI_CCU_GATE(H3_CLK_BUS_OHCI2, "bus-ohci2", "ahb2", - BUS_CLK_GATING_REG0, 30), - SUNXI_CCU_GATE(H3_CLK_BUS_OHCI3, "bus-ohci3", "ahb2", - BUS_CLK_GATING_REG0, 31), - SUNXI_CCU_GATE(H3_CLK_BUS_PIO, "bus-pio", "apb1", + SUNXI_CCU_GATE(A83T_CLK_BUS_PIO, "bus-pio", "apb1", BUS_CLK_GATING_REG2, 5), - SUNXI_CCU_GATE(H3_CLK_BUS_I2C0, "bus-i2c0", "apb2", + SUNXI_CCU_GATE(A83T_CLK_BUS_I2C0, "bus-i2c0", "apb2", BUS_CLK_GATING_REG3, 0), - SUNXI_CCU_GATE(H3_CLK_BUS_I2C1, "bus-i2c1", "apb2", + SUNXI_CCU_GATE(A83T_CLK_BUS_I2C1, "bus-i2c1", "apb2", BUS_CLK_GATING_REG3, 1), - SUNXI_CCU_GATE(H3_CLK_BUS_I2C2, "bus-i2c2", "apb2", + SUNXI_CCU_GATE(A83T_CLK_BUS_I2C2, "bus-i2c2", "apb2", BUS_CLK_GATING_REG3, 2), - SUNXI_CCU_GATE(H3_CLK_BUS_UART0, "bus-uart0", "apb2", + SUNXI_CCU_GATE(A83T_CLK_BUS_UART0, "bus-uart0", "apb2", BUS_CLK_GATING_REG3, 16), - SUNXI_CCU_GATE(H3_CLK_BUS_UART1, "bus-uart1", "apb2", + SUNXI_CCU_GATE(A83T_CLK_BUS_UART1, "bus-uart1", "apb2", BUS_CLK_GATING_REG3, 17), - SUNXI_CCU_GATE(H3_CLK_BUS_UART2, "bus-uart2", "apb2", + SUNXI_CCU_GATE(A83T_CLK_BUS_UART2, "bus-uart2", "apb2", BUS_CLK_GATING_REG3, 18), - SUNXI_CCU_GATE(H3_CLK_BUS_UART3, "bus-uart3", "apb2", + SUNXI_CCU_GATE(A83T_CLK_BUS_UART3, "bus-uart3", "apb2", BUS_CLK_GATING_REG3, 19), - SUNXI_CCU_GATE(H3_CLK_USBPHY0, "usb-phy0", "hosc", + SUNXI_CCU_GATE(A83T_CLK_USB_PHY0, "usb-phy0", "hosc", USBPHY_CFG_REG, 8), - SUNXI_CCU_GATE(H3_CLK_USBPHY1, "usb-phy1", "hosc", + SUNXI_CCU_GATE(A83T_CLK_USB_PHY1, "usb-phy1", "hosc", USBPHY_CFG_REG, 9), - SUNXI_CCU_GATE(H3_CLK_USBPHY2, "usb-phy2", "hosc", - USBPHY_CFG_REG, 10), - SUNXI_CCU_GATE(H3_CLK_USBPHY3, "usb-phy3", "hosc", - USBPHY_CFG_REG, 11), - SUNXI_CCU_GATE(H3_CLK_USBOHCI0, "usb-ohci0", "hosc", + SUNXI_CCU_GATE(A83T_CLK_USB_OHCI0, "usb-ohci0", "hosc", USBPHY_CFG_REG, 16), - SUNXI_CCU_GATE(H3_CLK_USBOHCI1, "usb-ohci1", "hosc", - USBPHY_CFG_REG, 17), - SUNXI_CCU_GATE(H3_CLK_USBOHCI2, "usb-ohci2", "hosc", - USBPHY_CFG_REG, 18), - SUNXI_CCU_GATE(H3_CLK_USBOHCI3, "usb-ohci3", "hosc", - USBPHY_CFG_REG, 19), }; static int Index: src/sys/arch/arm/sunxi/sun8i_a83t_ccu.h diff -u src/sys/arch/arm/sunxi/sun8i_a83t_ccu.h:1.1 src/sys/arch/arm/sunxi/sun8i_a83t_ccu.h:1.2 --- src/sys/arch/arm/sunxi/sun8i_a83t_ccu.h:1.1 Thu Jul 6 22:10:14 2017 +++ src/sys/arch/arm/sunxi/sun8i_a83t_ccu.h Sat Oct 28 12:07:40 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: sun8i_a83t_ccu.h,v 1.1 2017/07/06 22:10:14 jmcneill Exp $ */ +/* $NetBSD: sun8i_a83t_ccu.h,v 1.2 2017/10/28 12:07:40 jmcneill Exp $ */ /*- * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca> @@ -29,6 +29,152 @@ #ifndef _SUN8I_A83T_CCU_H #define _SUN8I_A83T_CCU_H -#include <arm/sunxi/sun8i_h3_ccu.h> +#define A83T_RST_USB_PHY0 0 +#define A83T_RST_USB_PHY1 1 +#define A83T_RST_USB_HSIC 2 +#define A83T_RST_DRAM 3 +#define A83T_RST_MBUS 4 +#define A83T_RST_BUS_MIPI_DSI 5 +#define A83T_RST_BUS_SS 6 +#define A83T_RST_BUS_DMA 7 +#define A83T_RST_BUS_MMC0 8 +#define A83T_RST_BUS_MMC1 9 +#define A83T_RST_BUS_MMC2 10 +#define A83T_RST_BUS_NAND 11 +#define A83T_RST_BUS_DRAM 12 +#define A83T_RST_BUS_EMAC 13 +#define A83T_RST_BUS_HSTIMER 14 +#define A83T_RST_BUS_SPI0 15 +#define A83T_RST_BUS_SPI1 16 +#define A83T_RST_BUS_OTG 17 +#define A83T_RST_BUS_EHCI0 18 +#define A83T_RST_BUS_EHCI1 19 +#define A83T_RST_BUS_OHCI0 20 +#define A83T_RST_BUS_VE 21 +#define A83T_RST_BUS_TCON0 22 +#define A83T_RST_BUS_TCON1 23 +#define A83T_RST_BUS_CSI 24 +#define A83T_RST_BUS_HDMI0 25 +#define A83T_RST_BUS_HDMI1 26 +#define A83T_RST_BUS_DE 27 +#define A83T_RST_BUS_GPU 28 +#define A83T_RST_BUS_MSGBOX 29 +#define A83T_RST_BUS_SPINLOCK 30 +#define A83T_RST_BUS_LVDS 31 +#define A83T_RST_BUS_SPDIF 32 +#define A83T_RST_BUS_I2S0 33 +#define A83T_RST_BUS_I2S1 34 +#define A83T_RST_BUS_I2S2 35 +#define A83T_RST_BUS_TDM 36 +#define A83T_RST_BUS_I2C0 37 +#define A83T_RST_BUS_I2C1 38 +#define A83T_RST_BUS_I2C2 39 +#define A83T_RST_BUS_UART0 40 +#define A83T_RST_BUS_UART1 41 +#define A83T_RST_BUS_UART2 42 +#define A83T_RST_BUS_UART3 43 +#define A83T_RST_BUS_UART4 44 + +#define A83T_CLK_PLL_C0CPUX 0 +#define A83T_CLK_PLL_C1CPUX 1 +#define A83T_CLK_PLL_AUDIO 2 +#define A83T_CLK_PLL_VIDEO0 3 +#define A83T_CLK_PLL_VE 4 +#define A83T_CLK_PLL_DDR 5 +#define A83T_CLK_PLL_PERIPH 6 +#define A83T_CLK_PLL_GPU 7 +#define A83T_CLK_PLL_HSIC 8 +#define A83T_CLK_PLL_DE 9 +#define A83T_CLK_PLL_VIDEO1 10 +#define A83T_CLK_C0CPUX 11 +#define A83T_CLK_C1CPUX 12 +#define A83T_CLK_AXI0 13 +#define A83T_CLK_AXI1 14 +#define A83T_CLK_AHB1 15 +#define A83T_CLK_AHB2 16 +#define A83T_CLK_APB1 17 +#define A83T_CLK_APB2 18 +#define A83T_CLK_BUS_MIPI_DSI 19 +#define A83T_CLK_BUS_SS 20 +#define A83T_CLK_BUS_DMA 21 +#define A83T_CLK_BUS_MMC0 22 +#define A83T_CLK_BUS_MMC1 23 +#define A83T_CLK_BUS_MMC2 24 +#define A83T_CLK_BUS_NAND 25 +#define A83T_CLK_BUS_DRAM 26 +#define A83T_CLK_BUS_EMAC 27 +#define A83T_CLK_BUS_HSTIMER 28 +#define A83T_CLK_BUS_SPI0 29 +#define A83T_CLK_BUS_SPI1 30 +#define A83T_CLK_BUS_OTG 31 +#define A83T_CLK_BUS_EHCI0 32 +#define A83T_CLK_BUS_EHCI1 33 +#define A83T_CLK_BUS_OHCI0 34 +#define A83T_CLK_BUS_VE 35 +#define A83T_CLK_BUS_TCON0 36 +#define A83T_CLK_BUS_TCON1 37 +#define A83T_CLK_BUS_CSI 38 +#define A83T_CLK_BUS_HDMI 39 +#define A83T_CLK_BUS_DE 40 +#define A83T_CLK_BUS_GPU 41 +#define A83T_CLK_BUS_MSGBOX 42 +#define A83T_CLK_BUS_SPINLOCK 43 +#define A83T_CLK_BUS_SPDIF 44 +#define A83T_CLK_BUS_PIO 45 +#define A83T_CLK_BUS_I2S0 46 +#define A83T_CLK_BUS_I2S1 47 +#define A83T_CLK_BUS_I2S2 48 +#define A83T_CLK_BUS_TDM 49 +#define A83T_CLK_BUS_I2C0 50 +#define A83T_CLK_BUS_I2C1 51 +#define A83T_CLK_BUS_I2C2 52 +#define A83T_CLK_BUS_UART0 53 +#define A83T_CLK_BUS_UART1 54 +#define A83T_CLK_BUS_UART2 55 +#define A83T_CLK_BUS_UART3 56 +#define A83T_CLK_BUS_UART4 57 +#define A83T_CLK_CCI400 58 +#define A83T_CLK_NAND 59 +#define A83T_CLK_MMC0 60 +#define A83T_CLK_MMC0_SAMPLE 61 +#define A83T_CLK_MMC0_OUTPUT 62 +#define A83T_CLK_MMC1 63 +#define A83T_CLK_MMC1_SAMPLE 64 +#define A83T_CLK_MMC1_OUTPUT 65 +#define A83T_CLK_MMC2 66 +#define A83T_CLK_MMC2_SAMPLE 67 +#define A83T_CLK_MMC2_OUTPUT 68 +#define A83T_CLK_SS 69 +#define A83T_CLK_SPI0 70 +#define A83T_CLK_SPI1 71 +#define A83T_CLK_I2S0 72 +#define A83T_CLK_I2S1 73 +#define A83T_CLK_I2S2 74 +#define A83T_CLK_TDM 75 +#define A83T_CLK_SPDIF 76 +#define A83T_CLK_USB_PHY0 77 +#define A83T_CLK_USB_PHY1 78 +#define A83T_CLK_USB_HSIC 79 +#define A83T_CLK_USB_HSIC_12M 80 +#define A83T_CLK_USB_OHCI0 81 +#define A83T_CLK_DRAM 82 +#define A83T_CLK_DRAM_VE 83 +#define A83T_CLK_DRAM_CSI 84 +#define A83T_CLK_TCON0 85 +#define A83T_CLK_TCON1 86 +#define A83T_CLK_CSI_MISC 87 +#define A83T_CLK_MIPI_CSI 88 +#define A83T_CLK_CSI_MCLK 89 +#define A83T_CLK_CSI_SCLK 90 +#define A83T_CLK_VE 91 +#define A83T_CLK_AVS 92 +#define A83T_CLK_HDMI 93 +#define A83T_CLK_HDMI_SLOW 94 +#define A83T_CLK_MBUS 95 +#define A83T_CLK_MIPI_DSI0 96 +#define A83T_CLK_MIPI_DSI1 97 +#define A83T_CLK_GPU_CORE 98 +#define A83T_CLK_GPU_MEMORY 99 +#define A83T_CLK_GPU_HYD 100 #endif /* !_SUN8I_A83T_CCU_H */