Module Name: src
Committed By: jmcneill
Date: Sun Oct 29 14:06:08 UTC 2017
Modified Files:
src/sys/dev/ic: com.c comreg.h comvar.h ns16550reg.h
Log Message:
Make all of the COM_xxx type options runtime selectable. Kernel configs
with the existing options (COM_16650, COM_16750, COM_AWIN, COM_HAYESP, and
COM_PXA2X0) will select the correct type in com_attach_subr. New code
should specify the com type by passing COM_TYPE_xxx to comcnattach and/or
setting sc_type.
To generate a diff of this commit:
cvs rdiff -u -r1.343 -r1.344 src/sys/dev/ic/com.c
cvs rdiff -u -r1.25 -r1.26 src/sys/dev/ic/comreg.h
cvs rdiff -u -r1.83 -r1.84 src/sys/dev/ic/comvar.h
cvs rdiff -u -r1.11 -r1.12 src/sys/dev/ic/ns16550reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/ic/com.c
diff -u src/sys/dev/ic/com.c:1.343 src/sys/dev/ic/com.c:1.344
--- src/sys/dev/ic/com.c:1.343 Sat Oct 28 04:53:55 2017
+++ src/sys/dev/ic/com.c Sun Oct 29 14:06:08 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: com.c,v 1.343 2017/10/28 04:53:55 riastradh Exp $ */
+/* $NetBSD: com.c,v 1.344 2017/10/29 14:06:08 jmcneill Exp $ */
/*-
* Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc.
@@ -66,7 +66,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: com.c,v 1.343 2017/10/28 04:53:55 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: com.c,v 1.344 2017/10/29 14:06:08 jmcneill Exp $");
#include "opt_com.h"
#include "opt_ddb.h"
@@ -122,9 +122,7 @@ __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.34
#include <dev/ic/comvar.h>
#include <dev/ic/ns16550reg.h>
#include <dev/ic/st16650reg.h>
-#ifdef COM_HAYESP
#include <dev/ic/hayespreg.h>
-#endif
#define com_lcr com_cfcr
#include <dev/cons.h>
@@ -252,20 +250,12 @@ void com_kgdb_putc(void *, int);
#ifdef COM_REGMAP
/* initializer for typical 16550-ish hardware */
-#define COM_REG_16550 { \
- com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \
- com_efr, com_lcr, com_mcr, com_lsr, com_msr }
-/* 16750-specific register set, additional UART status register */
-#define COM_REG_16750 { \
+#define COM_REG_STD { \
com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \
com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr }
-#ifdef COM_16750
-const bus_size_t com_std_map[32] = COM_REG_16750;
-#else
-const bus_size_t com_std_map[16] = COM_REG_16550;
-#endif /* COM_16750 */
+const bus_size_t com_std_map[32] = COM_REG_STD;
#endif /* COM_REGMAP */
#define COMDIALOUT_MASK TTDIALOUT_MASK
@@ -393,9 +383,7 @@ com_attach_subr(struct com_softc *sc)
{
struct com_regs *regsp = &sc->sc_regs;
struct tty *tp;
-#if defined(COM_16650) || defined(COM_16750)
u_int8_t lcr;
-#endif
const char *fifo_msg = NULL;
prop_dictionary_t dict;
bool is_console = true;
@@ -407,6 +395,18 @@ com_attach_subr(struct com_softc *sc)
callout_init(&sc->sc_diag_callout, 0);
mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);
+#if defined(COM_16650)
+ sc->sc_type = COM_TYPE_16650;
+#elif defined(COM_16750)
+ sc->sc_type = COM_TYPE_16750;
+#elif defined(COM_AWIN)
+ sc->sc_type = COM_TYPE_SUNXI;
+#elif defined(COM_HAYESP)
+ sc->sc_type = COM_TYPE_HAYESP;
+#elif defined(COM_PXA2X0)
+ sc->sc_type = COM_TYPE_PXA2x0;
+#endif
+
/* Disable interrupts before configuring the device. */
if (sc->sc_type == COM_TYPE_PXA2x0)
sc->sc_ier = IER_EUART;
@@ -424,10 +424,13 @@ com_attach_subr(struct com_softc *sc)
(u_long)comcons_info.regs.cr_iobase);
}
-#if defined(COM_16750) || defined(COM_AWIN)
- /* Use in comintr(). */
- sc->sc_lcr = cflag2lcr(comcons_info.cflag);
-#endif
+ switch (sc->sc_type) {
+ case COM_TYPE_16750:
+ case COM_TYPE_SUNXI:
+ /* Use in comintr(). */
+ sc->sc_lcr = cflag2lcr(comcons_info.cflag);
+ break;
+ }
/* Make sure the console is always "hardwired". */
delay(10000); /* wait for output to finish */
@@ -501,7 +504,8 @@ com_attach_subr(struct com_softc *sc)
== FIFO_TRIGGER_14) {
SET(sc->sc_hwflags, COM_HW_FIFO);
-#ifdef COM_16650
+ fifo_msg = "ns16550a, working fifo";
+
/*
* IIR changes into the EFR if LCR is set to LCR_EERS
* on 16650s. We also know IIR != 0 at this point.
@@ -513,23 +517,32 @@ com_attach_subr(struct com_softc *sc)
* setting DLAB enable gives access to the EFR on
* these chips.
*/
- lcr = CSR_READ_1(regsp, COM_REG_LCR);
- CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
- CSR_WRITE_1(regsp, COM_REG_EFR, 0);
- if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
- CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
+ if (sc->sc_type == COM_TYPE_16650) {
+ lcr = CSR_READ_1(regsp, COM_REG_LCR);
+ CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
+ CSR_WRITE_1(regsp, COM_REG_EFR, 0);
if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
- CLR(sc->sc_hwflags, COM_HW_FIFO);
- sc->sc_fifolen = 0;
- } else {
- SET(sc->sc_hwflags, COM_HW_FLOW);
- sc->sc_fifolen = 32;
- }
- } else
-#endif
- sc->sc_fifolen = 16;
+ CSR_WRITE_1(regsp, COM_REG_LCR,
+ lcr | LCR_DLAB);
+ if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
+ CLR(sc->sc_hwflags, COM_HW_FIFO);
+ sc->sc_fifolen = 0;
+ } else {
+ SET(sc->sc_hwflags, COM_HW_FLOW);
+ sc->sc_fifolen = 32;
+ }
+ } else
+ sc->sc_fifolen = 16;
+
+ CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
+ if (sc->sc_fifolen == 0)
+ fifo_msg = "st16650, broken fifo";
+ else if (sc->sc_fifolen == 32)
+ fifo_msg = "st16650a, working fifo";
+ else
+ fifo_msg = "ns16550a, working fifo";
+ }
-#ifdef COM_16750
/*
* TL16C750 can enable 64byte FIFO, only when DLAB
* is 1. However, some 16750 may always enable. For
@@ -539,54 +552,43 @@ com_attach_subr(struct com_softc *sc)
* use SC16C750. Probably 32 bytes of FIFO and HW FLOW
* should become effective.
*/
- uint8_t iir1, iir2;
- uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14;
-
- if (sc->sc_type == COM_TYPE_INGENIC)
- fcr |= FIFO_UART_ON;
-
- lcr = CSR_READ_1(regsp, COM_REG_LCR);
- CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB);
- CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE);
- iir1 = CSR_READ_1(regsp, COM_REG_IIR);
- CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
- CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
- CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE);
- iir2 = CSR_READ_1(regsp, COM_REG_IIR);
-
- CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
-
- if (!ISSET(iir1, IIR_64B_FIFO) &&
- ISSET(iir2, IIR_64B_FIFO)) {
- /* It is TL16C750. */
- sc->sc_fifolen = 64;
- SET(sc->sc_hwflags, COM_HW_AFE);
- } else
+ if (sc->sc_type == COM_TYPE_16750) {
+ uint8_t iir1, iir2;
+ uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14;
+
+ lcr = CSR_READ_1(regsp, COM_REG_LCR);
+ CSR_WRITE_1(regsp, COM_REG_LCR,
+ lcr & ~LCR_DLAB);
+ CSR_WRITE_1(regsp, COM_REG_FIFO,
+ fcr | FIFO_64B_ENABLE);
+ iir1 = CSR_READ_1(regsp, COM_REG_IIR);
CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
-#endif
+ CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
+ CSR_WRITE_1(regsp, COM_REG_FIFO,
+ fcr | FIFO_64B_ENABLE);
+ iir2 = CSR_READ_1(regsp, COM_REG_IIR);
+
+ CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
+
+ if (!ISSET(iir1, IIR_64B_FIFO) &&
+ ISSET(iir2, IIR_64B_FIFO)) {
+ /* It is TL16C750. */
+ sc->sc_fifolen = 64;
+ SET(sc->sc_hwflags, COM_HW_AFE);
+ } else
+ CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
-#ifdef COM_16650
- CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
- if (sc->sc_fifolen == 0)
- fifo_msg = "st16650, broken fifo";
- else if (sc->sc_fifolen == 32)
- fifo_msg = "st16650a, working fifo";
- else
-#endif
-#ifdef COM_16750
- if (sc->sc_fifolen == 64)
- fifo_msg = "tl16c750, working fifo";
- else
-#endif
- fifo_msg = "ns16550a, working fifo";
+ if (sc->sc_fifolen == 64)
+ fifo_msg = "tl16c750, working fifo";
+ else
+ fifo_msg = "ns16750, working fifo";
+ }
} else
fifo_msg = "ns16550, broken fifo";
else
fifo_msg = "ns8250 or ns16450, no fifo";
- if (sc->sc_type == COM_TYPE_INGENIC) {
- CSR_WRITE_1(regsp, COM_REG_FIFO, FIFO_UART_ON);
- } else
- CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
+ CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
+
fifodelay:
/*
* Some chips will clear down both Tx and Rx FIFOs when zero is
@@ -685,7 +687,6 @@ com_config(struct com_softc *sc)
CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
(void) CSR_READ_1(regsp, COM_REG_IIR);
-#ifdef COM_HAYESP
/* Look for a Hayes ESP board. */
if (sc->sc_type == COM_TYPE_HAYESP) {
@@ -716,7 +717,6 @@ com_config(struct com_softc *sc)
bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
HAYESP_LOBYTE(HAYESP_RXLOWMARK));
}
-#endif
if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB))
com_enable_debugport(sc);
@@ -1360,7 +1360,6 @@ comparam(struct tty *tp, struct termios
if (COM_ISALIVE(sc) == 0)
return (EIO);
-#ifdef COM_HAYESP
if (sc->sc_type == COM_TYPE_HAYESP) {
int prescaler, speed;
@@ -1378,8 +1377,7 @@ comparam(struct tty *tp, struct termios
return (EINVAL);
sc->sc_prescaler = prescaler;
} else
-#endif
- ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type);
+ ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type);
/* Check requested parameters. */
if (ospeed < 0)
@@ -1565,6 +1563,7 @@ void
com_iflush(struct com_softc *sc)
{
struct com_regs *regsp = &sc->sc_regs;
+ uint8_t fifo;
#ifdef DIAGNOSTIC
int reg;
#endif
@@ -1588,19 +1587,21 @@ com_iflush(struct com_softc *sc)
aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg);
#endif
-#if defined(COM_16750) || defined(COM_AWIN)
- uint8_t fifo;
- /*
- * Reset all Rx/Tx FIFO, preserve current FIFO length.
- * This should prevent triggering busy interrupt while
- * manipulating divisors.
- */
- fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 |
- FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14);
- CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST |
- FIFO_XMT_RST);
- delay(100);
-#endif
+ switch (sc->sc_type) {
+ case COM_TYPE_16750:
+ case COM_TYPE_SUNXI:
+ /*
+ * Reset all Rx/Tx FIFO, preserve current FIFO length.
+ * This should prevent triggering busy interrupt while
+ * manipulating divisors.
+ */
+ fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 |
+ FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14);
+ CSR_WRITE_1(regsp, COM_REG_FIFO,
+ fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST);
+ delay(100);
+ break;
+ }
}
void
@@ -1640,14 +1641,12 @@ com_loadchannelregs(struct com_softc *sc
CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr);
CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo);
-#ifdef COM_HAYESP
if (sc->sc_type == COM_TYPE_HAYESP) {
bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
HAYESP_SETPRESCALER);
bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
sc->sc_prescaler);
}
-#endif
if (sc->sc_type == COM_TYPE_OMAP) {
/* setup the fifos. the FCR value is not used as long
as SCR[6] and SCR[7] are 0, which they are at reset
@@ -1922,10 +1921,8 @@ com_rxsoft(struct com_softc *sc, struct
if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
SET(sc->sc_ier, IER_ERXRDY);
-#ifdef COM_PXA2X0
if (sc->sc_type == COM_TYPE_PXA2x0)
SET(sc->sc_ier, IER_ERXTOUT);
-#endif
if (sc->sc_type == COM_TYPE_INGENIC ||
sc->sc_type == COM_TYPE_TEGRA)
SET(sc->sc_ier, IER_ERXTOUT);
@@ -2034,13 +2031,9 @@ comintr(void *arg)
iir = CSR_READ_1(regsp, COM_REG_IIR);
/* Handle ns16750-specific busy interrupt. */
-#ifdef COM_16750
-#ifdef COM_AWIN
-#error "COM_16750 and COM_AWIN are exclusive"
-#endif
- int timeout;
- if ((iir & IIR_BUSY) == IIR_BUSY) {
- for (timeout = 10000;
+ if (sc->sc_type == COM_TYPE_16750 &&
+ (iir & IIR_BUSY) == IIR_BUSY) {
+ for (int timeout = 10000;
(CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--)
if (timeout <= 0) {
aprint_error_dev(sc->sc_dev,
@@ -2053,10 +2046,10 @@ comintr(void *arg)
CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
iir = CSR_READ_1(regsp, COM_REG_IIR);
}
-#endif /* COM_16750 */
-#ifdef COM_AWIN
+
/* Allwinner BUSY interrupt */
- if ((iir & IIR_BUSY) == IIR_BUSY) {
+ if (sc->sc_type == COM_TYPE_SUNXI &&
+ (iir & IIR_BUSY) == IIR_BUSY) {
if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) {
CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN);
CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
@@ -2086,7 +2079,6 @@ comintr(void *arg)
CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
}
}
-#endif /* COM_AWIN */
if (ISSET(iir, IIR_NOPEND)) {
mutex_spin_exit(&sc->sc_lock);
@@ -2166,17 +2158,19 @@ again: do {
*/
if (!cc) {
SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
-#ifdef COM_PXA2X0
- if (sc->sc_type == COM_TYPE_PXA2x0)
+ switch (sc->sc_type) {
+ case COM_TYPE_PXA2x0:
CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT);
- else
-#endif
- if (sc->sc_type == COM_TYPE_INGENIC ||
- sc->sc_type == COM_TYPE_TEGRA)
+ break;
+ case COM_TYPE_INGENIC:
+ case COM_TYPE_TEGRA:
CLR(sc->sc_ier,
IER_ERXRDY | IER_ERXTOUT);
- else
+ break;
+ default:
CLR(sc->sc_ier, IER_ERXRDY);
+ break;
+ }
CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
}
} else {
@@ -2444,11 +2438,9 @@ cominit(struct com_regs *regsp, int rate
}
}
-#ifdef COM_PXA2X0
if (type == COM_TYPE_PXA2x0)
CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
else
-#endif
CSR_WRITE_1(regsp, COM_REG_IER, 0);
return (0);
Index: src/sys/dev/ic/comreg.h
diff -u src/sys/dev/ic/comreg.h:1.25 src/sys/dev/ic/comreg.h:1.26
--- src/sys/dev/ic/comreg.h:1.25 Fri May 27 20:01:49 2016
+++ src/sys/dev/ic/comreg.h Sun Oct 29 14:06:08 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: comreg.h,v 1.25 2016/05/27 20:01:49 bouyer Exp $ */
+/* $NetBSD: comreg.h,v 1.26 2017/10/29 14:06:08 jmcneill Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -64,9 +64,7 @@
#define IIR_NOPEND 0x1 /* No pending interrupts */
#define IIR_64B_FIFO 0x20 /* 64byte FIFO Enabled (16750) */
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
-#if defined(COM_16750) || defined(COM_AWIN)
-#define IIR_BUSY 0x7 /* Busy indicator */
-#endif
+#define IIR_BUSY 0x7 /* Busy indicator (16750/SUNXI) */
/* fifo control register */
#define FIFO_ENABLE 0x01 /* Turn the FIFO on */
@@ -160,11 +158,9 @@
#define MDR1_MODE_UART_16X 0x00
#define MDR1_MODE_MASK 0x07
-#ifdef COM_AWIN
-/* AWIN-specific registers */
+/* SUNXI-specific registers */
#define HALT_CHCFG_UD 0x04 /* apply updates to LCR/dividors */
#define HALT_CHCFG_EN 0x02 /* enable change while busy */
-#endif
/* XXX ISA-specific. */
Index: src/sys/dev/ic/comvar.h
diff -u src/sys/dev/ic/comvar.h:1.83 src/sys/dev/ic/comvar.h:1.84
--- src/sys/dev/ic/comvar.h:1.83 Mon Jul 31 09:25:14 2017
+++ src/sys/dev/ic/comvar.h Sun Oct 29 14:06:08 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: comvar.h,v 1.83 2017/07/31 09:25:14 jmcneill Exp $ */
+/* $NetBSD: comvar.h,v 1.84 2017/10/29 14:06:08 jmcneill Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@@ -91,33 +91,20 @@ int com_is_console(bus_space_tag_t, bus_
#define COM_REG_MCR 9
#define COM_REG_LSR 10
#define COM_REG_MSR 11
-#ifdef COM_16750
-#define COM_REG_USR 31
-#endif
-#ifdef COM_AWIN
-#define COM_REG_USR 31
-#define COM_REG_TFL 32
-#define COM_REG_RFL 33
-#define COM_REG_HALT 41
-#endif
+#define COM_REG_USR 31 /* 16750/SUNXI */
+#define COM_REG_TFL 32 /* SUNXI */
+#define COM_REG_RFL 33 /* SUNXI */
+#define COM_REG_HALT 41 /* SUNXI */
struct com_regs {
bus_space_tag_t cr_iot;
bus_space_handle_t cr_ioh;
bus_addr_t cr_iobase;
bus_size_t cr_nports;
-#ifdef COM_16750
bus_size_t cr_map[32];
-#else
- bus_size_t cr_map[16];
-#endif
};
-#ifdef COM_16750
extern const bus_size_t com_std_map[32];
-#else
-extern const bus_size_t com_std_map[16];
-#endif
#define COM_INIT_REGS(regs, tag, hdl, addr) \
do { \
@@ -144,15 +131,10 @@ extern const bus_size_t com_std_map[16];
#define COM_REG_TCR com_msr
#define COM_REG_TLR com_scratch
#define COM_REG_MDR1 8
-#ifdef COM_16750
-#define COM_REG_USR com_usr
-#endif
-#ifdef COM_AWIN
-#define COM_REG_USR com_usr
-#define COM_REG_TFL com_tfl
-#define COM_REG_RFL com_rfl
-#define COM_REG_HALT com_halt
-#endif
+#define COM_REG_USR com_usr /* 16750/SUNXI */
+#define COM_REG_TFL com_tfl /* SUNXI */
+#define COM_REG_RFL com_rfl /* SUNXI */
+#define COM_REG_HALT com_halt /* SUNXI */
struct com_regs {
bus_space_tag_t cr_iot;
@@ -229,9 +211,7 @@ struct com_softc {
sc_mcr_active, sc_lcr, sc_ier, sc_fifo, sc_dlbl, sc_dlbh, sc_efr;
u_char sc_mcr_dtr, sc_mcr_rts, sc_msr_cts, sc_msr_dcd;
-#ifdef COM_HAYESP
- u_char sc_prescaler;
-#endif
+ u_char sc_prescaler; /* for COM_TYPE_HAYESP */
/*
* There are a great many almost-ns16550-compatible UARTs out
@@ -248,6 +228,9 @@ struct com_softc {
#define COM_TYPE_INGENIC 6 /* JZ4780 built-in */
#define COM_TYPE_TEGRA 7 /* NVIDIA Tegra built-in */
#define COM_TYPE_BCMAUXUART 8 /* BCM2835 AUX UART */
+#define COM_TYPE_16650 9
+#define COM_TYPE_16750 10
+#define COM_TYPE_SUNXI 11 /* Allwinner built-in */
/* power management hooks */
int (*enable)(struct com_softc *);
Index: src/sys/dev/ic/ns16550reg.h
diff -u src/sys/dev/ic/ns16550reg.h:1.11 src/sys/dev/ic/ns16550reg.h:1.12
--- src/sys/dev/ic/ns16550reg.h:1.11 Fri May 27 20:01:49 2016
+++ src/sys/dev/ic/ns16550reg.h Sun Oct 29 14:06:08 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: ns16550reg.h,v 1.11 2016/05/27 20:01:49 bouyer Exp $ */
+/* $NetBSD: ns16550reg.h,v 1.12 2017/10/29 14:06:08 jmcneill Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -51,12 +51,11 @@
/*
* Additional register present in NS16750
*/
-#ifdef COM_16750
-#define com_usr 31 /* status register (R) */
-#endif
-#ifdef COM_AWIN
-#define com_usr 31 /* status register (R) */
-#define com_tfl 32 /* transmit fifo level (R) */
-#define com_rfl 33 /* receive fifo level (R) */
-#define com_halt 41 /* halt tx (R/W) */
-#endif
+#define com_usr 31 /* status register (R) (16750/SUNXI) */
+
+/*
+ * Additional registers present on Allwinner hardware
+ */
+#define com_tfl 32 /* transmit fifo level (R) (SUNXI) */
+#define com_rfl 33 /* receive fifo level (R) (SUNXI) */
+#define com_halt 41 /* halt tx (R/W) (SUNXI) */
