Module Name: src
Committed By: martin
Date: Tue Nov 21 14:16:38 UTC 2017
Modified Files:
src/sys/dev/pci [netbsd-8]: pci_subr.c pcireg.h
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #362):
sys/dev/pci/pcireg.h: revision 1.133
sys/dev/pci/pcireg.h: revision 1.134
sys/dev/pci/pcireg.h: revision 1.135
sys/dev/pci/pci_subr.c: revision 1.190
sys/dev/pci/pci_subr.c: revision 1.191
sys/dev/pci/pci_subr.c: revision 1.192
sys/dev/pci/pci_subr.c: revision 1.193
sys/dev/pci/pci_subr.c: revision 1.194
sys/dev/pci/pcireg.h: revision 1.132
- Official shortname of LN Requester is LNR, so change PCI_EXTCAP_LN_REQ
to PCI_EXTCAP_LNR
- Use macro.
- Add PCI_MAPREG_ROM_ADDR_MASK macro and PCI_MAPREG_ROM_ADDR() macro.
- print PCI_MAPREG_ROM_ENABLE bit.
- Decode Expansion ROM Validation ECN.
- Add Native PCIe Enclosure Management ECN's extended capability type.
Not decoded yet.
Decode IOMMU capability of PCI secure device capability. From "AMD I/O
Virtualization Technology(IOMMU) Specification (#48882) Revision 3.00".
IOMMU cap dump fixes:
- Print Capability Register's value.
- Indent output correctly.
- s/cahced/cached/
- Print MSI Message number with 0x%02x
Fix a bug that the TPH ST table is decoded even if it's not in the TPH
Requester extended capability structure.
To generate a diff of this commit:
cvs rdiff -u -r1.183.2.1 -r1.183.2.2 src/sys/dev/pci/pci_subr.c
cvs rdiff -u -r1.130.2.1 -r1.130.2.2 src/sys/dev/pci/pcireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/pci_subr.c
diff -u src/sys/dev/pci/pci_subr.c:1.183.2.1 src/sys/dev/pci/pci_subr.c:1.183.2.2
--- src/sys/dev/pci/pci_subr.c:1.183.2.1 Tue Jul 4 14:35:21 2017
+++ src/sys/dev/pci/pci_subr.c Tue Nov 21 14:16:38 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.183.2.1 2017/07/04 14:35:21 martin Exp $ */
+/* $NetBSD: pci_subr.c,v 1.183.2.2 2017/11/21 14:16:38 martin Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183.2.1 2017/07/04 14:35:21 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183.2.2 2017/11/21 14:16:38 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -1530,7 +1530,91 @@ pci_conf_print_subsystem_cap(const pcire
}
/* XXX pci_conf_print_agp8_cap */
-/* XXX pci_conf_print_secure_cap */
+static void
+pci_conf_print_secure_cap(const pcireg_t *regs, int capoff)
+{
+ pcireg_t reg, reg2, val;
+ bool havemisc1;
+
+ printf("\n Secure Capability Register\n");
+ reg = regs[o2i(capoff + PCI_SECURE_CAP)];
+ printf(" Capability Register: 0x%04x\n", reg >> 16);
+ val = __SHIFTOUT(reg, PCI_SECURE_CAP_TYPE);
+ printf(" Capability block type: ");
+ /* I know IOMMU Only */
+ if (val == PCI_SECURE_CAP_TYPE_IOMMU)
+ printf("IOMMU\n");
+ else {
+ printf("0x%x(unknown)\n", val);
+ return;
+ }
+
+ val = __SHIFTOUT(reg, PCI_SECURE_CAP_REV);
+ printf(" Capability revision: 0x%02x ", val);
+ if (val == PCI_SECURE_CAP_REV_IOMMU)
+ printf("(IOMMU)\n");
+ else {
+ printf("(unknown)\n");
+ return;
+ }
+ onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP);
+ onoff("HyperTransport tunnel translation support", reg,
+ PCI_SECURE_CAP_HTTUNNEL);
+ onoff("Not present table entries cached", reg, PCI_SECURE_CAP_NPCACHE);
+ onoff("IOMMU Extended Feature Register support", reg,
+ PCI_SECURE_CAP_EFRSUP);
+ onoff("IOMMU Miscellaneous Information Register 1", reg,
+ PCI_SECURE_CAP_EXT);
+ havemisc1 = reg & PCI_SECURE_CAP_EXT;
+
+ reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)];
+ printf(" Base Address Low Register: 0x%08x\n", reg);
+ onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN);
+ reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)];
+ printf(" Base Address High Register: 0x%08x\n", reg2);
+ printf(" Base Address : 0x%016" PRIx64 "\n",
+ ((uint64_t)reg2 << 32)
+ | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L)));
+
+ reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)];
+ printf(" IOMMU Range Register: 0x%08x\n", reg);
+ printf(" HyperTransport UnitID: 0x%02x\n",
+ (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID));
+ onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID);
+ printf(" Device range bus number: 0x%02x\n",
+ (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM));
+ printf(" First device: 0x%04x\n",
+ (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV));
+ printf(" Last device: 0x%04x\n",
+ (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV));
+
+ reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)];
+ printf(" Miscellaneous Information Register 0: 0x%08x\n", reg);
+ printf(" MSI Message number: 0x%02x\n",
+ (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM));
+ val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE);
+ printf(" Guest Virtual Address size: ");
+ if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B)
+ printf("48bits\n");
+ else
+ printf("0x%x(unknown)\n", val);
+ val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE);
+ printf(" Physical Address size: %dbits\n", val);
+ val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE);
+ printf(" Virtual Address size: %dbits\n", val);
+ onoff("ATS response address range reserved", reg,
+ PCI_SECURE_IOMMU_MISC0_ATSRESV);
+ printf(" Peripheral Page Request MSI Message number: 0x%02x\n",
+ (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR));
+
+ if (!havemisc1)
+ return;
+
+ reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)];
+ printf(" Miscellaneous Information Register 1: 0x%08x\n", reg);
+ printf(" MSI Message number (GA): 0x%02x\n",
+ (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM));
+}
static void
pci_print_pcie_L0s_latency(uint32_t val)
@@ -2087,7 +2171,7 @@ pci_conf_print_pcie_cap(const pcireg_t *
break;
}
printf(" OBFF Supported: ");
- switch ((reg & PCIE_DCAP2_OBFF) >> 18) {
+ switch (__SHIFTOUT(reg, PCIE_DCAP2_OBFF)) {
case 0x0:
printf("Not supported\n");
break;
@@ -2139,7 +2223,7 @@ pci_conf_print_pcie_cap(const pcireg_t *
onoff("Emergency Power Reduction Request", reg,
PCIE_DCSR2_EMGPWRRED_REQ);
printf(" OBFF: ");
- switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) {
+ switch (__SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) {
case 0x0:
printf("Disabled\n");
break;
@@ -2352,7 +2436,7 @@ static struct {
{ PCI_CAP_SUBVENDOR, "Subsystem vendor ID",
pci_conf_print_subsystem_cap },
{ PCI_CAP_AGP8, "AGP 8x", NULL },
- { PCI_CAP_SECURE, "Secure Device", NULL },
+ { PCI_CAP_SECURE, "Secure Device", pci_conf_print_secure_cap },
{ PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap },
{ PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap },
{ PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap },
@@ -3415,15 +3499,15 @@ pci_conf_print_dpa_cap(const pcireg_t *r
}
static const char *
-pci_conf_print_tph_req_cap_sttabloc(unsigned char val)
+pci_conf_print_tph_req_cap_sttabloc(uint8_t val)
{
switch (val) {
- case 0x0:
+ case PCI_TPH_REQ_STTBLLOC_NONE:
return "Not Present";
- case 0x1:
+ case PCI_TPH_REQ_STTBLLOC_TPHREQ:
return "in the TPH Requester Capability Structure";
- case 0x2:
+ case PCI_TPH_REQ_STTBLLOC_MSIX:
return "in the MSI-X Table";
default:
return "Unknown";
@@ -3435,6 +3519,7 @@ pci_conf_print_tph_req_cap(const pcireg_
{
pcireg_t reg;
int size, i, j;
+ uint8_t sttbloc;
printf("\n TPH Requester Extended Capability\n");
@@ -3444,9 +3529,9 @@ pci_conf_print_tph_req_cap(const pcireg_
onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC);
onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC);
onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ);
+ sttbloc = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC);
printf(" ST Table Location: %s\n",
- pci_conf_print_tph_req_cap_sttabloc(
- (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC)));
+ pci_conf_print_tph_req_cap_sttabloc(sttbloc));
size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1;
printf(" ST Table Size: %d\n", size);
@@ -3482,7 +3567,10 @@ pci_conf_print_tph_req_cap(const pcireg_
printf("(reserved vaule)\n");
break;
}
-
+
+ if (sttbloc != PCI_TPH_REQ_STTBLLOC_TPHREQ)
+ return;
+
for (i = 0; i < size ; i += 2) {
reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)];
for (j = 0; j < 2 ; j++) {
@@ -3873,6 +3961,7 @@ pci_conf_print_ptm_cap(const pcireg_t *r
/* XXX pci_conf_print_desigvndsp_cap */
/* XXX pci_conf_print_vf_resizbar_cap */
/* XXX pci_conf_print_hierarchyid_cap */
+/* XXX pci_conf_print_npem_cap */
#undef MS
#undef SM
@@ -3939,7 +4028,7 @@ static struct {
NULL },
{ PCI_EXTCAP_PASID, "Process Address Space ID",
pci_conf_print_pasid_cap },
- { PCI_EXTCAP_LN_REQ, "LN Requester",
+ { PCI_EXTCAP_LNR, "LN Requester",
pci_conf_print_lnr_cap },
{ PCI_EXTCAP_DPC, "Downstream Port Containment",
pci_conf_print_dpc_cap },
@@ -3959,6 +4048,8 @@ static struct {
NULL },
{ PCI_EXTCAP_HIERARCHYID, "Hierarchy ID",
NULL },
+ { PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management",
+ NULL },
};
static int
@@ -4099,6 +4190,7 @@ pci_conf_print_type0(
{
int off, width;
pcireg_t rval;
+ const char *str;
for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) {
#ifdef _KERNEL
@@ -4115,9 +4207,43 @@ pci_conf_print_type0(
printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
- /* XXX */
- printf(" Expansion ROM Base Address: 0x%08x\n",
- regs[o2i(PCI_MAPREG_ROM)]);
+ rval = regs[o2i(PCI_MAPREG_ROM)];
+ printf(" Expansion ROM Base Address Register: 0x%08x\n", rval);
+ printf(" base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval));
+ onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE);
+ printf(" Validation Status: ");
+ switch (__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) {
+ case PCI_MAPREG_ROM_VSTAT_NOTSUPP:
+ str = "Validation not supported";
+ break;
+ case PCI_MAPREG_ROM_VSTAT_INPROG:
+ str = "Validation in Progress";
+ break;
+ case PCI_MAPREG_ROM_VSTAT_VPASS:
+ str = "Validation Pass. "
+ "Valid contents, trust test was not performed";
+ break;
+ case PCI_MAPREG_ROM_VSTAT_VPASSTRUST:
+ str = "Validation Pass. Valid and trusted contents";
+ break;
+ case PCI_MAPREG_ROM_VSTAT_VFAIL:
+ str = "Validation Fail. Invalid contents";
+ break;
+ case PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST:
+ str = "Validation Fail. Valid but untrusted contents";
+ break;
+ case PCI_MAPREG_ROM_VSTAT_WPASS:
+ str = "Warning Pass. Validation passed with warning. "
+ "Valid contents, trust test was not performed";
+ break;
+ case PCI_MAPREG_ROM_VSTAT_WPASSTRUST:
+ str = "Warning Pass. Validation passed with warning. "
+ "Valid and trusted contents";
+ break;
+ }
+ printf("%s\n", str);
+ printf(" Validation Details: 0x%x\n",
+ (uint32_t)__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL));
if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
printf(" Capability list pointer: 0x%02x\n",
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.130.2.1 src/sys/dev/pci/pcireg.h:1.130.2.2
--- src/sys/dev/pci/pcireg.h:1.130.2.1 Tue Jul 4 14:35:21 2017
+++ src/sys/dev/pci/pcireg.h Tue Nov 21 14:16:38 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.130.2.1 2017/07/04 14:35:21 martin Exp $ */
+/* $NetBSD: pcireg.h,v 1.130.2.2 2017/11/21 14:16:38 martin Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -485,6 +485,20 @@ typedef u_int8_t pci_revision_t;
(PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc
+#define PCI_MAPREG_ROM_ADDR(mr) \
+ ((mr) & PCI_MAPREG_ROM_ADDR_MASK)
+#define PCI_MAPREG_ROM_VALID_STAT __BITS(3, 1) /* Validation Status */
+#define PCI_MAPREG_ROM_VSTAT_NOTSUPP 0x0 /* Validation not supported */
+#define PCI_MAPREG_ROM_VSTAT_INPROG 0x1 /* Validation in Progress */
+#define PCI_MAPREG_ROM_VSTAT_VPASS 0x2 /* Valid contnt, trust test nperf*/
+#define PCI_MAPREG_ROM_VSTAT_VPASSTRUST 0x3 /* Valid and trusted contents */
+#define PCI_MAPREG_ROM_VSTAT_VFAIL 0x4 /* Invaild contents */
+#define PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST 0x5 /* Vaild but untrusted contents*/
+#define PCI_MAPREG_ROM_VSTAT_WPASS 0x6 /* VPASS + warning */
+#define PCI_MAPREG_ROM_VSTAT_WPASSTRUST 0x7 /* VPASSTRUST + warning */
+#define PCI_MAPREG_ROM_VALID_DETAIL __BITS(7, 4) /* Validation Details */
+#define PCI_MAPREG_ROM_ADDR_MASK __BITS(31, 11)
+
#define PCI_MAPREG_SIZE_TO_MASK(size) \
(-(size))
@@ -886,8 +900,43 @@ typedef u_int8_t pci_revision_t;
/*
* Capability ID: 0x0f
- * Secure
+ * Secure Device
+ *
+ * Reference: AMD I/O Virtualization Technology(IOMMU) Specification (#48882)
+ * Revision 3.00.
*/
+#define PCI_SECURE_CAP 0x00 /* Capability Header */
+#define PCI_SECURE_CAP_TYPE __BITS(18, 16) /* Capability block type */
+#define PCI_SECURE_CAP_TYPE_IOMMU 0x3 /* IOMMU Cap */
+#define PCI_SECURE_CAP_REV __BITS(23, 19) /* Capability revision */
+#define PCI_SECURE_CAP_REV_IOMMU 0x01 /* IOMMU interface */
+/* For IOMMU only */
+#define PCI_SECURE_CAP_IOTLBSUP __BIT(24) /* IOTLB */
+#define PCI_SECURE_CAP_HTTUNNEL __BIT(25) /* HT tunnel translation */
+#define PCI_SECURE_CAP_NPCACHE __BIT(26) /* Not present table entries cahced*/
+#define PCI_SECURE_CAP_EFRSUP __BIT(27) /* IOMMU Ext-Feature Reg */
+#define PCI_SECURE_CAP_EXT __BIT(28) /* IOMMU Misc Info Reg 1 */
+#define PCI_SECURE_IOMMU_BAL 0x04 /* Base Address Low */
+#define PCI_SECURE_IOMMU_BAL_EN __BIT(0) /* Enable */
+#define PCI_SECURE_IOMMU_BAL_L __BITS(18, 14) /* Base Addr [18:14] */
+#define PCI_SECURE_IOMMU_BAL_H __BITS(31, 19) /* Base Addr [31:19] */
+#define PCI_SECURE_IOMMU_BAH 0x08 /* Base Address High */
+#define PCI_SECURE_IOMMU_RANGE 0x0c /* IOMMU Range */
+#define PCI_SECURE_IOMMU_RANGE_UNITID __BITS(4, 0) /* HT UnitID */
+#define PCI_SECURE_IOMMU_RANGE_RNGVALID __BIT(7) /* Range valid */
+#define PCI_SECURE_IOMMU_RANGE_BUSNUM __BITS(15, 8) /* bus number */
+#define PCI_SECURE_IOMMU_RANGE_FIRSTDEV __BITS(23, 16) /* First device */
+#define PCI_SECURE_IOMMU_RANGE_LASTDEV __BITS(31, 24) /* Last device */
+#define PCI_SECURE_IOMMU_MISC0 0x10 /* IOMMU Miscellaneous Information 0 */
+#define PCI_SECURE_IOMMU_MISC0_MSINUM __BITS(4, 0) /* MSI Message number */
+#define PCI_SECURE_IOMMU_MISC0_GVASIZE __BITS(7, 5) /* Guest Virtual Adr siz */
+#define PCI_SECURE_IOMMU_MISC0_GVASIZE_48B 0x2 /* 48bits */
+#define PCI_SECURE_IOMMU_MISC0_PASIZE __BITS(14, 8) /* Physical Address siz */
+#define PCI_SECURE_IOMMU_MISC0_VASIZE __BITS(21, 15)/* Virtual Address size */
+#define PCI_SECURE_IOMMU_MISC0_ATSRESV __BIT(22) /* ATS resp addr range rsvd */
+#define PCI_SECURE_IOMMU_MISC0_MISNPPR __BITS(31, 27)/* Periph Pg Rq MSI Msgn*/
+#define PCI_SECURE_IOMMU_MISC1 0x14 /* IOMMU Miscellaneous Information 1 */
+#define PCI_SECURE_IOMMU_MISC1_MSINUM __BITS(4, 0) /* MSI Messsage number(GA)*/
/*
* Capability ID: 0x10
@@ -1433,7 +1482,7 @@ struct pci_rom {
#define PCI_EXTCAP_SEC_PCIE 0x0019 /* Secondary PCI Express */
#define PCI_EXTCAP_PMUX 0x001a /* Protocol Multiplexing */
#define PCI_EXTCAP_PASID 0x001b /* Process Address Space ID */
-#define PCI_EXTCAP_LN_REQ 0x001c /* LN Requester */
+#define PCI_EXTCAP_LNR 0x001c /* LN Requester */
#define PCI_EXTCAP_DPC 0x001d /* Downstream Port Containment */
#define PCI_EXTCAP_L1PM 0x001e /* L1 PM Substates */
#define PCI_EXTCAP_PTM 0x001f /* Precision Time Management */
@@ -1443,6 +1492,7 @@ struct pci_rom {
#define PCI_EXTCAP_DESIGVNDSP 0x0023 /* Designated Vendor-Specific */
#define PCI_EXTCAP_VF_RESIZBAR 0x0024 /* VF Resizable BAR */
#define PCI_EXTCAP_HIERARCHYID 0x0028 /* Hierarchy ID */
+#define PCI_EXTCAP_NPEM 0x0029 /* Native PCIe Enclosure Management */
/*
* Extended capability ID: 0x0001
@@ -1854,6 +1904,9 @@ struct pci_rom {
#define PCI_TPH_REQ_CAP_DEVSPEC __BIT(2) /* Device Specific Mode Supported */
#define PCI_TPH_REQ_CAP_XTPHREQ __BIT(8) /* Extend TPH Reqester Supported */
#define PCI_TPH_REQ_CAP_STTBLLOC __BITS(10, 9) /* ST Table Location */
+#define PCI_TPH_REQ_STTBLLOC_NONE 0 /* not present */
+#define PCI_TPH_REQ_STTBLLOC_TPHREQ 1 /* in the TPHREQ cap */
+#define PCI_TPH_REQ_STTBLLOC_MSIX 2 /* in the MSI-X table */
#define PCI_TPH_REQ_CAP_STTBLSIZ __BITS(26, 16) /* ST Table Size */
#define PCI_TPH_REQ_CTL 0x08 /* TPH Requester Control */
#define PCI_TPH_REQ_CTL_STSEL __BITS(2, 0) /* ST Mode Select */
@@ -2042,4 +2095,14 @@ struct pci_rom {
* VF Resizable BAR
*/
+/*
+ * Extended capability ID: 0x0028
+ * Hierarchy ID
+ */
+
+/*
+ * Extended capability ID: 0x0029
+ * Native PCIe Enclosure Management
+ */
+
#endif /* _DEV_PCI_PCIREG_H_ */
