Module Name: src
Committed By: jmcneill
Date: Sun Feb 18 10:28:37 UTC 2018
Modified Files:
src/sys/arch/arm/sunxi: files.sunxi sunxi_gpio.h
Added Files:
src/sys/arch/arm/sunxi: sun50i_h6_gpio.c
Log Message:
Add support for Allwinner H6 CPUX and CPUS port controllers.
To generate a diff of this commit:
cvs rdiff -u -r1.41 -r1.42 src/sys/arch/arm/sunxi/files.sunxi
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/sunxi/sun50i_h6_gpio.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/sunxi/sunxi_gpio.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/sunxi/files.sunxi
diff -u src/sys/arch/arm/sunxi/files.sunxi:1.41 src/sys/arch/arm/sunxi/files.sunxi:1.42
--- src/sys/arch/arm/sunxi/files.sunxi:1.41 Wed Feb 14 20:10:17 2018
+++ src/sys/arch/arm/sunxi/files.sunxi Sun Feb 18 10:28:37 2018
@@ -1,4 +1,4 @@
-# $NetBSD: files.sunxi,v 1.41 2018/02/14 20:10:17 jakllsch Exp $
+# $NetBSD: files.sunxi,v 1.42 2018/02/18 10:28:37 jmcneill Exp $
#
# Configuration info for Allwinner sunxi family SoCs
#
@@ -105,6 +105,7 @@ file arch/arm/sunxi/sun8i_a83t_gpio.c su
file arch/arm/sunxi/sun8i_h3_gpio.c sunxi_gpio & (soc_sun8i_h3 | soc_sun50i_h5)
file arch/arm/sunxi/sun9i_a80_gpio.c sunxi_gpio & soc_sun9i_a80
file arch/arm/sunxi/sun50i_a64_gpio.c sunxi_gpio & soc_sun50i_a64
+file arch/arm/sunxi/sun50i_h6_gpio.c sunxi_gpio & soc_sun50i_h6
# UART
attach com at fdt with sunxi_com
@@ -253,3 +254,4 @@ defflag opt_soc.h SOC_SUN9I_A80: SOC_S
defflag opt_soc.h SOC_SUN50I: SOC_SUNXI
defflag opt_soc.h SOC_SUN50I_A64: SOC_SUN50I
defflag opt_soc.h SOC_SUN50I_H5: SOC_SUN50I
+defflag opt_soc.h SOC_SUN50I_H6: SOC_SUN50I
Index: src/sys/arch/arm/sunxi/sunxi_gpio.h
diff -u src/sys/arch/arm/sunxi/sunxi_gpio.h:1.7 src/sys/arch/arm/sunxi/sunxi_gpio.h:1.8
--- src/sys/arch/arm/sunxi/sunxi_gpio.h:1.7 Sun Oct 8 18:00:36 2017
+++ src/sys/arch/arm/sunxi/sunxi_gpio.h Sun Feb 18 10:28:37 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_gpio.h,v 1.7 2017/10/08 18:00:36 jmcneill Exp $ */
+/* $NetBSD: sunxi_gpio.h,v 1.8 2018/02/18 10:28:37 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -88,4 +88,9 @@ extern const struct sunxi_gpio_padconf s
extern const struct sunxi_gpio_padconf sun50i_a64_r_padconf;
#endif
+#ifdef SOC_SUN50I_H6
+extern const struct sunxi_gpio_padconf sun50i_h6_padconf;
+extern const struct sunxi_gpio_padconf sun50i_h6_r_padconf;
+#endif
+
#endif /* _ARM_SUNXI_GPIO_H */
Added files:
Index: src/sys/arch/arm/sunxi/sun50i_h6_gpio.c
diff -u /dev/null src/sys/arch/arm/sunxi/sun50i_h6_gpio.c:1.1
--- /dev/null Sun Feb 18 10:28:37 2018
+++ src/sys/arch/arm/sunxi/sun50i_h6_gpio.c Sun Feb 18 10:28:37 2018
@@ -0,0 +1,151 @@
+/* $NetBSD: sun50i_h6_gpio.c,v 1.1 2018/02/18 10:28:37 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2016 Jared McNeill <jmcne...@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: sun50i_h6_gpio.c,v 1.1 2018/02/18 10:28:37 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/types.h>
+
+#include <arm/sunxi/sunxi_gpio.h>
+
+static const struct sunxi_gpio_pins h6_pins[] = {
+ { "PC0", 2, 0, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } },
+ { "PC1", 2, 1, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC2", 2, 2, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } },
+ { "PC3", 2, 3, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } },
+ { "PC4", 2, 4, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC5", 2, 5, { "gpio_in", "gpio_out", "nand", "mmc2", "spi0" } },
+ { "PC6", 2, 6, { "gpio_in", "gpio_out", "nand", "mmc2", "spi0" } },
+ { "PC7", 2, 7, { "gpio_in", "gpio_out", "nand", "mmc2", "spi0" } },
+ { "PC8", 2, 8, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC9", 2, 9, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC10", 2, 10, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC11", 2, 11, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC12", 2, 12, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC13", 2, 13, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC14", 2, 14, { "gpio_in", "gpio_out", "nand", "mmc2" } },
+ { "PC15", 2, 15, { "gpio_in", "gpio_out", "nand" } },
+ { "PC16", 2, 16, { "gpio_in", "gpio_out", "nand" } },
+
+ { "PD0", 3, 0, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
+ { "PD1", 3, 1, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
+ { "PD2", 3, 2, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
+ { "PD3", 3, 3, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
+ { "PD4", 3, 4, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
+ { "PD5", 3, 5, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
+ { "PD6", 3, 6, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
+ { "PD7", 3, 7, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
+ { "PD8", 3, 8, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
+ { "PD9", 3, 9, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
+ { "PD10", 3, 10, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
+ { "PD11", 3, 11, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } },
+ { "PD12", 3, 12, { "gpio_in", "gpio_out", "lcd0", "ts1", "csi", "emac" } },
+ { "PD13", 3, 13, { "gpio_in", "gpio_out", "lcd0", "ts1", "csi", "emac" } },
+ { "PD14", 3, 14, { "gpio_in", "gpio_out", "lcd0", "ts1", "dmic", "csi" } },
+ { "PD15", 3, 15, { "gpio_in", "gpio_out", "lcd0", "ts1", "dmic", "csi" } },
+ { "PD16", 3, 16, { "gpio_in", "gpio_out", "lcd0", "ts1", "dmic" } },
+ { "PD17", 3, 17, { "gpio_in", "gpio_out", "lcd0", "ts2", "dmic" } },
+ { "PD18", 3, 18, { "gpio_in", "gpio_out", "lcd0", "ts2", "dmic" } },
+ { "PD19", 3, 19, { "gpio_in", "gpio_out", "lcd0", "ts2", "uart2", "emac" } },
+ { "PD20", 3, 20, { "gpio_in", "gpio_out", "lcd0", "ts2", "uart2", "emac" } },
+ { "PD21", 3, 21, { "gpio_in", "gpio_out", "lcd0", "ts2", "uart2" } },
+ { "PD22", 3, 22, { "gpio_in", "gpio_out", "pwm0", "ts3", "uart2" } },
+ { "PD23", 3, 23, { "gpio_in", "gpio_out", "i2c2", "ts3", "uart3", "jtag" } },
+ { "PD24", 3, 24, { "gpio_in", "gpio_out", "i2c2", "ts3", "uart3", "jtag" } },
+ { "PD25", 3, 25, { "gpio_in", "gpio_out", "i2c0", "ts3", "uart3", "jtag" } },
+ { "PD26", 3, 26, { "gpio_in", "gpio_out", "i2c0", "ts3", "uart3", "jtag" } },
+
+ { "PF0", 5, 0, { "gpio_in", "gpio_out", "mmc0", "jtag" } },
+ { "PF1", 5, 1, { "gpio_in", "gpio_out", "mmc0", "jtag" } },
+ { "PF2", 5, 2, { "gpio_in", "gpio_out", "mmc0", "uart0" } },
+ { "PF3", 5, 3, { "gpio_in", "gpio_out", "mmc0", "jtag" } },
+ { "PF4", 5, 4, { "gpio_in", "gpio_out", "mmc0", "uart0" } },
+ { "PF5", 5, 5, { "gpio_in", "gpio_out", "mmc0", "jtag" } },
+ { "PF6", 5, 6, { "gpio_in", "gpio_out" } },
+
+ { "PG0", 6, 0, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint0" }, 6, 0 },
+ { "PG1", 6, 1, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint1" }, 6, 1 },
+ { "PG2", 6, 2, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint2" }, 6, 2 },
+ { "PG3", 6, 3, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint3" }, 6, 3 },
+ { "PG4", 6, 4, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint4" }, 6, 4 },
+ { "PG5", 6, 5, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint5" }, 6, 5 },
+ { "PG6", 6, 6, { "gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "pg_eint6" }, 6, 6 },
+ { "PG7", 6, 7, { "gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "pg_eint7" }, 6, 7 },
+ { "PG8", 6, 8, { "gpio_in", "gpio_out", "uart1", "sim0", NULL, NULL, "pg_eint8" }, 6, 8 },
+ { "PG9", 6, 9, { "gpio_in", "gpio_out", "uart1", "sim0", NULL, NULL, "pg_eint9" }, 6, 9 },
+ { "PG10", 6, 10, { "gpio_in", "gpio_out", "i2s2", "h_i2s2", "sim0", NULL, "pg_eint10" }, 6, 10 },
+ { "PG11", 6, 11, { "gpio_in", "gpio_out", "i2s2", "h_i2s2", "sim0", NULL, "pg_eint11" }, 6, 11 },
+ { "PG12", 6, 12, { "gpio_in", "gpio_out", "i2s2", "h_i2s2", "sim0", NULL, "pg_eint12" }, 6, 12 },
+ { "PG13", 6, 13, { "gpio_in", "gpio_out", "i2s2", "h_i2s2", "sim0", NULL, "pg_eint13" }, 6, 13 },
+ { "PG14", 6, 14, { "gpio_in", "gpio_out", "i2s2", "h_i2s2", "sim0", NULL, "pg_eint14" }, 6, 13 },
+
+ { "PH0", 7, 0, { "gpio_in", "gpio_out", "uart0", "i2s0", "h_i2s0", "sim1", "ph_eint0" }, 6, 0 },
+ { "PH1", 7, 1, { "gpio_in", "gpio_out", "uart0", "i2s0", "h_i2s0", "sim1", "ph_eint1" }, 6, 1 },
+ { "PH2", 7, 2, { "gpio_in", "gpio_out", "cir", "i2s0", "h_i2s0", "sim1", "ph_eint2" }, 6, 2 },
+ { "PH3", 7, 3, { "gpio_in", "gpio_out", "spi1", "i2s0", "h_i2s0", "sim1", "ph_eint3" }, 6, 3 },
+ { "PH4", 7, 4, { "gpio_in", "gpio_out", "spi1", "i2s0", "h_i2s0", "sim1", "ph_eint4" }, 6, 4 },
+ { "PH5", 7, 5, { "gpio_in", "gpio_out", "spi1", "spdif", "i2c1", "sim1", "ph_eint5" }, 6, 5 },
+ { "PH6", 7, 6, { "gpio_in", "gpio_out", "spi1", "spdif", "i2c1", "sim1", "ph_eint6" }, 6, 6 },
+ { "PH7", 7, 7, { "gpio_in", "gpio_out", NULL, "spdif", NULL, NULL, "ph_eint7" }, 6, 7 },
+ { "PH8", 7, 8, { "gpio_in", "gpio_out", "hdmi", NULL, NULL, NULL, "ph_eint8" }, 6, 8 },
+ { "PH9", 7, 9, { "gpio_in", "gpio_out", "hdmi", NULL, NULL, NULL, "ph_eint9" }, 6, 9 },
+ { "PH10", 7, 10, { "gpio_in", "gpio_out", "hdmi", NULL, NULL, NULL, "ph_eint10" }, 6, 10 },
+};
+
+static const struct sunxi_gpio_pins h6_r_pins[] = {
+ { "PL0", 0, 0, { "gpio_in", "gpio_out", NULL, "s_i2c", NULL, NULL, "pl_eint0" }, 6, 0 },
+ { "PL1", 0, 1, { "gpio_in", "gpio_out", NULL, "s_i2c", NULL, NULL, "pl_eint1" }, 6, 1 },
+ { "PL2", 0, 2, { "gpio_in", "gpio_out", "s_uart", NULL, NULL, NULL, "pl_eint2" }, 6, 2 },
+ { "PL3", 0, 3, { "gpio_in", "gpio_out", "s_uart", NULL, NULL, NULL, "pl_eint3" }, 6, 3 },
+ { "PL4", 0, 4, { "gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "pl_eint4" }, 6, 4 },
+ { "PL5", 0, 5, { "gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "pl_eint5" }, 6, 5 },
+ { "PL6", 0, 6, { "gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "pl_eint6" }, 6, 6 },
+ { "PL7", 0, 7, { "gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "pl_eint7" }, 6, 7 },
+ { "PL8", 0, 8, { "gpio_in", "gpio_out", "s_i2s", NULL, NULL, NULL, "pl_eint8" }, 6, 8 },
+ { "PL9", 0, 9, { "gpio_in", "gpio_out", "s_cir", NULL, NULL, NULL, "pl_eint9" }, 6, 9 },
+ { "PL10", 0, 10, { "gpio_in", "gpio_out", "s_spdif", NULL, NULL, NULL, "pl_eint10" }, 6, 10 },
+
+ { "PM0", 1, 0, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "pm_eint0" }, 6, 0 },
+ { "PM1", 1, 1, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "pm_eint1" }, 6, 1 },
+ { "PM2", 1, 2, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "pm_eint2" }, 6, 2 },
+ { "PM3", 1, 3, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "pm_eint3" }, 6, 3 },
+ { "PM4", 1, 4, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "pm_eint4" }, 6, 4 },
+};
+
+const struct sunxi_gpio_padconf sun50i_h6_padconf = {
+ .npins = __arraycount(h6_pins),
+ .pins = h6_pins,
+};
+
+const struct sunxi_gpio_padconf sun50i_h6_r_padconf = {
+ .npins = __arraycount(h6_r_pins),
+ .pins = h6_r_pins,
+};
