Module Name: src
Committed By: skrll
Date: Sat Mar 3 18:11:25 UTC 2018
Modified Files:
src/sys/arch/arm/arm32: bus_dma.c
Log Message:
Rely on the cache operations to perform the necessary barriers.
To generate a diff of this commit:
cvs rdiff -u -r1.103 -r1.104 src/sys/arch/arm/arm32/bus_dma.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/bus_dma.c
diff -u src/sys/arch/arm/arm32/bus_dma.c:1.103 src/sys/arch/arm/arm32/bus_dma.c:1.104
--- src/sys/arch/arm/arm32/bus_dma.c:1.103 Sat Mar 3 16:16:24 2018
+++ src/sys/arch/arm/arm32/bus_dma.c Sat Mar 3 18:11:25 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_dma.c,v 1.103 2018/03/03 16:16:24 skrll Exp $ */
+/* $NetBSD: bus_dma.c,v 1.104 2018/03/03 18:11:25 skrll Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "opt_arm_bus_space.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.103 2018/03/03 16:16:24 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.104 2018/03/03 18:11:25 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -867,13 +867,11 @@ _bus_dmamap_sync_segment(vaddr_t va, pad
*/
case BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE:
STAT_INCR(sync_postreadwrite);
- arm_dmb();
cpu_dcache_inv_range(va, len);
cpu_sdcache_inv_range(va, pa, len);
break;
case BUS_DMASYNC_POSTREAD:
STAT_INCR(sync_postread);
- arm_dmb();
cpu_dcache_inv_range(va, len);
cpu_sdcache_inv_range(va, pa, len);
break;
