Module Name:    src
Committed By:   martin
Date:           Mon Apr 16 14:25:49 UTC 2018

Modified Files:
        src/share/man/man4 [netbsd-8]: wm.4
        src/sys/dev/pci [netbsd-8]: if_wm.c if_wmreg.h if_wmvar.h

Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #764):

        sys/dev/pci/if_wm.c: revision 1.567
        sys/dev/pci/if_wm.c: revision 1.568
        sys/dev/pci/if_wm.c: revision 1.569
        sys/dev/pci/if_wmvar.h: revision 1.38
        sys/dev/pci/if_wm.c: revision 1.570
        sys/dev/pci/if_wm.c: revision 1.571
        sys/dev/pci/if_wm.c: revision 1.572
        share/man/man4/wm.4: revision 1.40
        sys/dev/pci/if_wmreg.h: revision 1.106
        sys/dev/pci/if_wmreg.h: revision 1.107

SW PHY Config Enable bit for ICH8 B0 stepping is not bit 1 but bit 0.

 No binary change:
- Sort registers.
- Lowercase hexadecimal value.

 On PCH_SPT (and newer), FLASH access should be done by 32bit.
Especially for ICH_FLASH_HSFCTL register, it's located at 0x0006, so
it should be accessed via ICH_FLASH_HSFSTS(0x0004) and use shift or mask.

 Our PCH_SPT part of wm_nvm_valid_bank_detect_ich8lan() was based on
FreeBSD r287467. After that, they reverted it and committed the different
code in r287762. r287762's bank detect code didn't work for us because our wm
dirver had a problem in flash access. The problem was fixed in if_wm.c rev.
1.567, so we can use the new way now.

 If the extended configration size in the EXTCNFSIZE register is 0, don't
continue.
 Add PCH_CNP support (I219 with Intel 300 series chipset).
It's required more test, so it's disabled by default.

 Enable I219.

 I354 uses an external PHY, so don't use wm_set_eee_i350().


To generate a diff of this commit:
cvs rdiff -u -r1.36.4.1 -r1.36.4.2 src/share/man/man4/wm.4
cvs rdiff -u -r1.508.4.16 -r1.508.4.17 src/sys/dev/pci/if_wm.c
cvs rdiff -u -r1.98.6.3 -r1.98.6.4 src/sys/dev/pci/if_wmreg.h
cvs rdiff -u -r1.33.6.1 -r1.33.6.2 src/sys/dev/pci/if_wmvar.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/share/man/man4/wm.4
diff -u src/share/man/man4/wm.4:1.36.4.1 src/share/man/man4/wm.4:1.36.4.2
--- src/share/man/man4/wm.4:1.36.4.1	Mon Feb  5 15:07:30 2018
+++ src/share/man/man4/wm.4	Mon Apr 16 14:25:49 2018
@@ -1,4 +1,4 @@
-.\"	$NetBSD: wm.4,v 1.36.4.1 2018/02/05 15:07:30 martin Exp $
+.\"	$NetBSD: wm.4,v 1.36.4.2 2018/04/16 14:25:49 martin Exp $
 .\"
 .\" Copyright 2002, 2003 Wasabi Systems, Inc.
 .\" All rights reserved.
@@ -33,7 +33,7 @@
 .\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 .\" POSSIBILITY OF SUCH DAMAGE.
 .\"
-.Dd January 18, 2018
+.Dd April 13, 2018
 .Dt WM 4
 .Os
 .Sh NAME
@@ -152,6 +152,8 @@ Intel I210 Ethernet (Copper, Fiber)
 Intel I211 Ethernet
 .It
 Intel I217 and I218 Ethernet
+.It
+Intel I219 Ethernet (with Intel [123]00 series chipset)
 .El
 .Pp
 In addition to Intel's own

Index: src/sys/dev/pci/if_wm.c
diff -u src/sys/dev/pci/if_wm.c:1.508.4.16 src/sys/dev/pci/if_wm.c:1.508.4.17
--- src/sys/dev/pci/if_wm.c:1.508.4.16	Tue Mar  6 10:59:04 2018
+++ src/sys/dev/pci/if_wm.c	Mon Apr 16 14:25:49 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: if_wm.c,v 1.508.4.16 2018/03/06 10:59:04 martin Exp $	*/
+/*	$NetBSD: if_wm.c,v 1.508.4.17 2018/04/16 14:25:49 martin Exp $	*/
 
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -83,7 +83,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.508.4.16 2018/03/06 10:59:04 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.508.4.17 2018/04/16 14:25:49 martin Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_net_mpsafe.h"
@@ -1485,7 +1485,6 @@ static const struct wm_product {
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_LM3,
 	  "I218 LM Ethernet Connection",
 	  WM_T_PCH_LPT,		WMP_F_COPPER },
-#if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V,
 	  "I219 V Ethernet Connection",
 	  WM_T_PCH_SPT,		WMP_F_COPPER },
@@ -1513,7 +1512,18 @@ static const struct wm_product {
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM5,
 	  "I219 LM Ethernet Connection",
 	  WM_T_PCH_SPT,		WMP_F_COPPER },
-#endif
+	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V6,
+	  "I219 V Ethernet Connection",
+	  WM_T_PCH_CNP,		WMP_F_COPPER },
+	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V7,
+	  "I219 V Ethernet Connection",
+	  WM_T_PCH_CNP,		WMP_F_COPPER },
+	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM6,
+	  "I219 LM Ethernet Connection",
+	  WM_T_PCH_CNP,		WMP_F_COPPER },
+	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM7,
+	  "I219 LM Ethernet Connection",
+	  WM_T_PCH_CNP,		WMP_F_COPPER },
 	{ 0,			0,
 	  NULL,
 	  0,			0 },
@@ -1986,7 +1996,8 @@ alloc_retry:
 		    && (sc->sc_type != WM_T_PCH)
 		    && (sc->sc_type != WM_T_PCH2)
 		    && (sc->sc_type != WM_T_PCH_LPT)
-		    && (sc->sc_type != WM_T_PCH_SPT)) {
+		    && (sc->sc_type != WM_T_PCH_SPT)
+		    && (sc->sc_type != WM_T_PCH_CNP)) {
 			/* ICH* and PCH* have no PCIe capability registers */
 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
 				PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff,
@@ -2233,6 +2244,7 @@ alloc_retry:
 		sc->nvm.release = wm_put_nvm_ich8lan;
 		break;
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		sc->nvm.read = wm_nvm_read_spt;
 		/* SPT has no GFPREG; flash registers mapped through BAR0 */
 		sc->sc_flags |= WM_F_EEPROM_FLASH;
@@ -2468,6 +2480,7 @@ alloc_retry:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		/* XXX The funcid should be checked on some devices */
 		apme_mask = WUC_APME;
 		eeprom_data = CSR_READ(sc, WMREG_WUC);
@@ -2577,7 +2590,8 @@ alloc_retry:
 	if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9
 	    || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH
 	    || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT
-	    || sc->sc_type == WM_T_PCH_SPT || sc->sc_type == WM_T_82573
+	    || sc->sc_type == WM_T_PCH_SPT || sc->sc_type == WM_T_PCH_CNP
+	    || sc->sc_type == WM_T_82573
 	    || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) {
 		/* Copper only */
 	} else if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
@@ -2731,6 +2745,7 @@ alloc_retry:
 	case WM_T_PCH2:	/* PCH2 supports 9K frame size */
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		/* XXX limited to 9234 */
 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
 		break;
@@ -3374,6 +3389,7 @@ wm_set_ral(struct wm_softc *sc, const ui
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		if (idx == 0) {
 			CSR_WRITE(sc, WMREG_CORDOVA_RAL(idx), ral_lo);
 			CSR_WRITE_FLUSH(sc);
@@ -3431,7 +3447,7 @@ wm_mchash(struct wm_softc *sc, const uin
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
-	    || (sc->sc_type == WM_T_PCH_SPT)) {
+	    || (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP)){
 		hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
 		    (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
 		return (hash & 0x3ff);
@@ -3486,7 +3502,8 @@ wm_set_filter(struct wm_softc *sc)
 		size = WM_RAL_TABSIZE_ICH8;
 	else if (sc->sc_type == WM_T_PCH2)
 		size = WM_RAL_TABSIZE_PCH2;
-	else if ((sc->sc_type == WM_T_PCH_LPT) ||(sc->sc_type == WM_T_PCH_SPT))
+	else if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
+	    || (sc->sc_type == WM_T_PCH_CNP))
 		size = WM_RAL_TABSIZE_PCH_LPT;
 	else if (sc->sc_type == WM_T_82575)
 		size = WM_RAL_TABSIZE_82575;
@@ -3498,7 +3515,8 @@ wm_set_filter(struct wm_softc *sc)
 		size = WM_RAL_TABSIZE;
 	wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0);
 
-	if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)) {
+	if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
+	    || (sc->sc_type == WM_T_PCH_CNP)) {
 		i = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM), FWSM_WLOCK_MAC);
 		switch (i) {
 		case 0:
@@ -3523,7 +3541,7 @@ wm_set_filter(struct wm_softc *sc)
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
-	    || (sc->sc_type == WM_T_PCH_SPT))
+	    || (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP))
 		size = WM_ICH8_MC_TABSIZE;
 	else
 		size = WM_MC_TABSIZE;
@@ -3556,7 +3574,8 @@ wm_set_filter(struct wm_softc *sc)
 		    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 		    || (sc->sc_type == WM_T_PCH2)
 		    || (sc->sc_type == WM_T_PCH_LPT)
-		    || (sc->sc_type == WM_T_PCH_SPT))
+		    || (sc->sc_type == WM_T_PCH_SPT)
+		    || (sc->sc_type == WM_T_PCH_CNP))
 			reg &= 0x1f;
 		else
 			reg &= 0x7f;
@@ -3698,6 +3717,7 @@ wm_lan_init_done(struct wm_softc *sc)
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) {
 			reg = CSR_READ(sc, WMREG_STATUS);
 			if ((reg & STATUS_LAN_INIT_DONE) != 0)
@@ -3784,6 +3804,7 @@ wm_get_cfg_done(struct wm_softc *sc)
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		delay(10*1000);
 		if (sc->sc_type >= WM_T_ICH10)
 			wm_lan_init_done(sc);
@@ -3903,6 +3924,7 @@ wm_init_lcd_from_nvm(struct wm_softc *sc
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M;
 		break;
 	default:
@@ -3931,6 +3953,8 @@ wm_init_lcd_from_nvm(struct wm_softc *sc
 	
 	reg = CSR_READ(sc, WMREG_EXTCNFSIZE);
 	cnf_size = __SHIFTOUT(reg, EXTCNFSIZE_LENGTH);
+	if (cnf_size == 0)
+		goto release;
 
 	if (((sc->sc_type == WM_T_PCH)
 		&& ((extcnfctr & EXTCNFCTR_OEM_WRITE_ENABLE) == 0))
@@ -4113,6 +4137,7 @@ wm_initialize_hardware_bits(struct wm_so
 		case WM_T_PCH2:
 		case WM_T_PCH_LPT:
 		case WM_T_PCH_SPT:
+		case WM_T_PCH_CNP:
 			/* TARC0 */
 			if (sc->sc_type == WM_T_ICH8) {
 				/* Set TARC0 bits 29 and 28 */
@@ -4420,9 +4445,10 @@ wm_reset(struct wm_softc *sc)
 		    PBA_14K : PBA_10K;
 		break;
 	case WM_T_PCH:
-	case WM_T_PCH2:
+	case WM_T_PCH2:	/* XXX 14K? */
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		sc->sc_pba = PBA_26K;
 		break;
 	default:
@@ -4547,6 +4573,7 @@ wm_reset(struct wm_softc *sc)
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
 		if (wm_phy_resetisblocked(sc) == false) {
 			/*
@@ -4678,6 +4705,7 @@ wm_reset(struct wm_softc *sc)
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		break;
 	default:
 		panic("%s: unknown type\n", __func__);
@@ -4726,7 +4754,7 @@ wm_reset(struct wm_softc *sc)
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
-	    || (sc->sc_type == WM_T_PCH_SPT)) {
+	    || (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP)){
 		reg = CSR_READ(sc, WMREG_KABGTXD);
 		reg |= KABGTXD_BGSQLBIAS;
 		CSR_WRITE(sc, WMREG_KABGTXD, reg);
@@ -4735,7 +4763,12 @@ wm_reset(struct wm_softc *sc)
 	/* reload sc_ctrl */
 	sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
 
-	if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211))
+	if (sc->sc_type == WM_T_I354) {
+#if 0
+		/* I354 uses an external PHY */
+		wm_set_eee_i354(sc);
+#endif
+	} else if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211))
 		wm_set_eee_i350(sc);
 
 	/*
@@ -5409,7 +5442,7 @@ wm_init_locked(struct ifnet *ifp)
 	if ((sc->sc_flags & WM_F_HAS_AMT) != 0)
 		wm_get_hw_control(sc);
 
-	if ((sc->sc_type == WM_T_PCH_SPT) &&
+	if ((sc->sc_type >= WM_T_PCH_SPT) &&
 	    pci_intr_type(sc->sc_pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_INTX)
 		wm_legacy_irq_quirk_spt(sc);
 
@@ -5480,7 +5513,7 @@ wm_init_locked(struct ifnet *ifp)
 	if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
 	    && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH)
 	    && (sc->sc_type != WM_T_PCH2) && (sc->sc_type != WM_T_PCH_LPT)
-	    && (sc->sc_type != WM_T_PCH_SPT)) {
+	    && (sc->sc_type != WM_T_PCH_SPT) && (sc->sc_type != WM_T_PCH_CNP)){
 		CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
 		CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
 		CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
@@ -5515,6 +5548,7 @@ wm_init_locked(struct ifnet *ifp)
 		case WM_T_PCH2:
 		case WM_T_PCH_LPT:
 		case WM_T_PCH_SPT:
+		case WM_T_PCH_CNP:
 			/*
 			 * Set the mac to wait the maximum time between each
 			 * iteration and increase the max iterations when
@@ -5851,6 +5885,7 @@ wm_init_locked(struct ifnet *ifp)
 		break;
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		reg = CSR_READ(sc, WMREG_PBECCSTS);
 		reg |= PBECCSTS_UNCORR_ECC_ENABLE;
 		CSR_WRITE(sc, WMREG_PBECCSTS, reg);
@@ -8657,8 +8692,7 @@ wm_linkintr_gmii(struct wm_softc *sc, ui
 		 * on power up.
 		 * Set the Beacon Duration for I217 to 8 usec
 		 */
-		if ((sc->sc_type == WM_T_PCH_LPT)
-		    || (sc->sc_type == WM_T_PCH_SPT)) {
+		if (sc->sc_type >= WM_T_PCH_LPT) {
 			reg = CSR_READ(sc, WMREG_FEXTNVM4);
 			reg &= ~FEXTNVM4_BEACON_DURATION;
 			reg |= FEXTNVM4_BEACON_DURATION_8US;
@@ -8668,8 +8702,7 @@ wm_linkintr_gmii(struct wm_softc *sc, ui
 		/* XXX Work-around I218 hang issue */
 		/* e1000_k1_workaround_lpt_lp() */
 
-		if ((sc->sc_type == WM_T_PCH_LPT)
-		    || (sc->sc_type == WM_T_PCH_SPT)) {
+		if (sc->sc_type >= WM_T_PCH_LPT) {
 			/*
 			 * Set platform power management values for Latency
 			 * Tolerance Reporting (LTR)
@@ -9274,6 +9307,7 @@ wm_gmii_reset(struct wm_softc *sc)
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		/* generic reset */
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
 		CSR_WRITE_FLUSH(sc);
@@ -9332,6 +9366,7 @@ wm_gmii_reset(struct wm_softc *sc)
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		wm_phy_post_reset(sc);
 		break;
 	default:
@@ -9558,7 +9593,7 @@ wm_gmii_setup_phytype(struct wm_softc *s
 		new_readreg = wm_gmii_bm_readreg;
 		new_writereg = wm_gmii_bm_writereg;
 	}
-	if ((sc->sc_type >= WM_T_PCH) && (sc->sc_type <= WM_T_PCH_SPT)) {
+	if ((sc->sc_type >= WM_T_PCH) && (sc->sc_type <= WM_T_PCH_CNP)) {
 		/* All PCH* use _hv_ */
 		new_readreg = wm_gmii_hv_readreg;
 		new_writereg = wm_gmii_hv_writereg;
@@ -9676,7 +9711,8 @@ wm_gmii_mediainit(struct wm_softc *sc, p
 
 	/* get PHY control from SMBus to PCIe */
 	if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
-	    || (sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT))
+	    || (sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
+	    || (sc->sc_type == WM_T_PCH_CNP))
 		wm_smbustopci(sc);
 
 	wm_gmii_reset(sc);
@@ -9730,8 +9766,10 @@ wm_gmii_mediainit(struct wm_softc *sc, p
 	 * If the MAC is PCH2 or PCH_LPT and failed to detect MII PHY, call
 	 * wm_set_mdio_slow_mode_hv() for a workaround and retry.
 	 */
-	if (((sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) &&
-	    (LIST_FIRST(&mii->mii_phys) == NULL)) {
+	if (((sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
+		|| (sc->sc_type == WM_T_PCH_SPT)
+		|| (sc->sc_type == WM_T_PCH_CNP))
+	    && (LIST_FIRST(&mii->mii_phys) == NULL)) {
 		wm_set_mdio_slow_mode_hv(sc);
 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
@@ -11933,24 +11971,40 @@ wm_nvm_valid_bank_detect_ich8lan(struct 
 	uint32_t eecd;
 	uint32_t act_offset = ICH_NVM_SIG_WORD * 2 + 1;
 	uint32_t bank1_offset = sc->sc_ich8_flash_bank_size * sizeof(uint16_t);
+	uint32_t nvm_dword = 0;
 	uint8_t sig_byte = 0;
+ 	int rv;
 
 	switch (sc->sc_type) {
 	case WM_T_PCH_SPT:
-		/*
-		 * In SPT, read from the CTRL_EXT reg instead of accessing the
-		 * sector valid bits from the NVM.
-		 */
-		*bank = CSR_READ(sc, WMREG_CTRL_EXT) & CTRL_EXT_NVMVS;
-		if ((*bank == 0) || (*bank == 1)) {
-			aprint_error_dev(sc->sc_dev,
-			    "%s: no valid NVM bank present (%u)\n", __func__,
-				*bank);
-			return -1;
-		} else {
-			*bank = *bank - 2;
+	case WM_T_PCH_CNP:
+		bank1_offset = sc->sc_ich8_flash_bank_size * 2;
+		act_offset = ICH_NVM_SIG_WORD * 2;
+
+		/* set bank to 0 in case flash read fails. */
+		*bank = 0;
+
+		/* Check bank 0 */
+		rv = wm_read_ich8_dword(sc, act_offset, &nvm_dword);
+		if (rv != 0)
+			return rv;
+		sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8);
+		if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
+			*bank = 0;
+			return 0;
+		}
+
+		/* Check bank 1 */
+		rv = wm_read_ich8_dword(sc, act_offset + bank1_offset,
+		    &nvm_dword);
+		sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8);
+		if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
+			*bank = 1;
 			return 0;
 		}
+		aprint_error_dev(sc->sc_dev,
+		    "%s: no valid NVM bank present (%u)\n", __func__, *bank);
+		return -1;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 		eecd = CSR_READ(sc, WMREG_EECD);
@@ -11997,7 +12051,10 @@ wm_ich8_cycle_init(struct wm_softc *sc)
 	int32_t error = 1;
 	int32_t i     = 0;
 
-	hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
+	if (sc->sc_type >= WM_T_PCH_SPT)
+		hsfsts = ICH8_FLASH_READ32(sc, ICH_FLASH_HSFSTS) & 0xffffUL;
+	else
+		hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
 
 	/* May be check the Flash Des Valid bit in Hw status */
 	if ((hsfsts & HSFSTS_FLDVAL) == 0) {
@@ -12008,7 +12065,10 @@ wm_ich8_cycle_init(struct wm_softc *sc)
 	/* Clear DAEL in Hw status by writing a 1 */
 	hsfsts |= HSFSTS_ERR | HSFSTS_DAEL;
 
-	ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
+	if (sc->sc_type >= WM_T_PCH_SPT)
+		ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS, hsfsts & 0xffffUL);
+	else
+		ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
 
 	/*
 	 * Either we should have a hardware SPI cycle in progress bit to check
@@ -12029,7 +12089,11 @@ wm_ich8_cycle_init(struct wm_softc *sc)
 
 		/* Begin by setting Flash Cycle Done. */
 		hsfsts |= HSFSTS_DONE;
-		ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
+		if (sc->sc_type >= WM_T_PCH_SPT)
+			ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS,
+			    hsfsts & 0xffffUL);
+		else
+			ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
 		error = 0;
 	} else {
 		/*
@@ -12037,7 +12101,12 @@ wm_ich8_cycle_init(struct wm_softc *sc)
 		 * chance to end before giving up.
 		 */
 		for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
-			hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
+			if (sc->sc_type >= WM_T_PCH_SPT)
+				hsfsts = ICH8_FLASH_READ32(sc,
+				    ICH_FLASH_HSFSTS) & 0xffffUL;
+			else
+				hsfsts = ICH8_FLASH_READ16(sc,
+				    ICH_FLASH_HSFSTS);
 			if ((hsfsts & HSFSTS_FLINPRO) == 0) {
 				error = 0;
 				break;
@@ -12050,7 +12119,12 @@ wm_ich8_cycle_init(struct wm_softc *sc)
 			 * now set the Flash Cycle Done.
 			 */
 			hsfsts |= HSFSTS_DONE;
-			ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
+			if (sc->sc_type >= WM_T_PCH_SPT)
+				ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS,
+				    hsfsts & 0xffffUL);
+			else
+				ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS,
+				    hsfsts);
 		}
 	}
 	return error;
@@ -12070,13 +12144,24 @@ wm_ich8_flash_cycle(struct wm_softc *sc,
 	uint32_t i = 0;
 
 	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
-	hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
+	if (sc->sc_type >= WM_T_PCH_SPT)
+		hsflctl = ICH8_FLASH_READ32(sc, ICH_FLASH_HSFSTS) >> 16;
+	else
+		hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
 	hsflctl |= HSFCTL_GO;
-	ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
+	if (sc->sc_type >= WM_T_PCH_SPT)
+		ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS,
+		    (uint32_t)hsflctl << 16);
+	else
+		ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
 
 	/* Wait till FDONE bit is set to 1 */
 	do {
-		hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
+		if (sc->sc_type >= WM_T_PCH_SPT)
+			hsfsts = ICH8_FLASH_READ32(sc, ICH_FLASH_HSFSTS)
+			    & 0xffffUL;
+		else
+			hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
 		if (hsfsts & HSFSTS_DONE)
 			break;
 		delay(1);
@@ -12121,18 +12206,22 @@ wm_read_ich8_data(struct wm_softc *sc, u
 		if (error)
 			break;
 
-		hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
+		if (sc->sc_type >= WM_T_PCH_SPT)
+			hsflctl = ICH8_FLASH_READ32(sc, ICH_FLASH_HSFSTS)
+			    >> 16;
+		else
+			hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
 		hsflctl |=  ((size - 1) << HSFCTL_BCOUNT_SHIFT)
 		    & HSFCTL_BCOUNT_MASK;
 		hsflctl |= ICH_CYCLE_READ << HSFCTL_CYCLE_SHIFT;
-		if (sc->sc_type == WM_T_PCH_SPT) {
+		if (sc->sc_type >= WM_T_PCH_SPT) {
 			/*
 			 * In SPT, This register is in Lan memory space, not
 			 * flash. Therefore, only 32 bit access is supported.
 			 */
-			ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFCTL,
-			    (uint32_t)hsflctl);
+			ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS,
+			    (uint32_t)hsflctl << 16);
 		} else
 			ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
 
@@ -12168,7 +12257,13 @@ wm_read_ich8_data(struct wm_softc *sc, u
 			 * detected, it won't hurt to give it another try...
 			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
 			 */
-			hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
+			if (sc->sc_type >= WM_T_PCH_SPT)
+				hsfsts = ICH8_FLASH_READ32(sc,
+				    ICH_FLASH_HSFSTS) & 0xffffUL;
+			else
+				hsfsts = ICH8_FLASH_READ16(sc,
+				    ICH_FLASH_HSFSTS);
+					
 			if (hsfsts & HSFSTS_ERR) {
 				/* Repeat for some time before giving up. */
 				continue;
@@ -12526,7 +12621,8 @@ wm_nvm_validate_checksum(struct wm_softc
 		return 0;
 
 #ifdef WM_DEBUG
-	if (sc->sc_type == WM_T_PCH_LPT) {
+	if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
+	    || (sc->sc_type == WM_T_PCH_CNP)) {
 		csum_wordaddr = NVM_OFF_COMPAT;
 		valid_checksum = NVM_COMPAT_VALID_CHECKSUM;
 	} else {
@@ -13289,6 +13385,7 @@ wm_check_mng_mode(struct wm_softc *sc)
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		rv = wm_check_mng_mode_ich8lan(sc);
 		break;
 	case WM_T_82574:
@@ -13408,6 +13505,7 @@ wm_phy_resetisblocked(struct wm_softc *s
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		do {
 			reg = CSR_READ(sc, WMREG_FWSM);
 			if ((reg & FWSM_RSPCIPHY) == 0) {
@@ -13516,6 +13614,7 @@ wm_smbustopci(struct wm_softc *sc)
 	switch (sc->sc_type) {
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		if (wm_phy_is_accessible_pchlan(sc))
 			break;
 
@@ -13658,6 +13757,7 @@ wm_get_wakeup(struct wm_softc *sc)
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		sc->sc_flags |= WM_F_HAS_AMT;
 		sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
 		break;
@@ -13858,6 +13958,7 @@ wm_enable_wakeup(struct wm_softc *sc)
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		/* Disable gig during WOL */
 		reg = CSR_READ(sc, WMREG_PHY_CTRL);
 		reg |= PHY_CTRL_D0A_LPLU | PHY_CTRL_GBE_DIS;
@@ -14025,6 +14126,7 @@ wm_lplu_d0_disable(struct wm_softc *sc)
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
+	case WM_T_PCH_CNP:
 		reg = wm_gmii_hv_readreg(sc->sc_dev, 1, HV_OEM_BITS);
 		reg &= ~(HV_OEM_BITS_A1KDIS | HV_OEM_BITS_LPLU);
 		if (wm_phy_resetisblocked(sc) == false)
@@ -14367,7 +14469,7 @@ wm_phy_is_accessible_pchlan(struct wm_so
 		return false;
 	}
 out:
-	if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)) {
+	if (sc->sc_type >= WM_T_PCH_LPT) {
 		/* Only unforce SMBus if ME is not active */
 		if ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) == 0) {
 			/* Unforce SMBus mode in PHY */

Index: src/sys/dev/pci/if_wmreg.h
diff -u src/sys/dev/pci/if_wmreg.h:1.98.6.3 src/sys/dev/pci/if_wmreg.h:1.98.6.4
--- src/sys/dev/pci/if_wmreg.h:1.98.6.3	Fri Nov 24 08:39:09 2017
+++ src/sys/dev/pci/if_wmreg.h	Mon Apr 16 14:25:49 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: if_wmreg.h,v 1.98.6.3 2017/11/24 08:39:09 martin Exp $	*/
+/*	$NetBSD: if_wmreg.h,v 1.98.6.4 2018/04/16 14:25:49 martin Exp $	*/
 
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
@@ -511,15 +511,15 @@ struct livengood_tcpip_ctxdesc {
 #define EECD_SEC1VAL	(1U << 22)	/* Sector One Valid */
 #define EECD_SEC1VAL_VALMASK (EECD_EE_AUTORD | EECD_EE_PRES) /* Valid Mask */
 
+#define	WMREG_FEXTNVM6	0x0010	/* Future Extended NVM 6 */
+#define	FEXTNVM6_K1_OFF_ENABLE	__BIT(31)
+
 #define	WMREG_EERD	0x0014	/* EEPROM read */
 #define	EERD_DONE	0x02    /* done bit */
 #define	EERD_START	0x01	/* First bit for telling part to start operation */
 #define	EERD_ADDR_SHIFT	2	/* Shift to the address bits */
 #define	EERD_DATA_SHIFT	16	/* Offset to data in EEPROM read/write registers */
 
-#define	WMREG_FEXTNVM6	0x0010	/* Future Extended NVM 6 */
-#define	FEXTNVM6_K1_OFF_ENABLE	__BIT(31)
-
 #define	WMREG_CTRL_EXT	0x0018	/* Extended Device Control Register */
 #define	CTRL_EXT_NSICR		__BIT(0) /* Non Interrupt clear on read */
 #define	CTRL_EXT_GPI_EN(x)	(1U << (x)) /* gpin interrupt enable */
@@ -544,14 +544,14 @@ struct livengood_tcpip_ctxdesc {
 #define	CTRL_EXT_SDLPE		(1U << 18) /* SerDes Low Power Enable */
 #define	CTRL_EXT_DMA_DYN_CLK	(1U << 19) /* DMA Dynamic Gating Enable */
 #define	CTRL_EXT_PHYPDEN	__BIT(20)
-#define	CTRL_EXT_LINK_MODE_MASK		0x00C00000
+#define	CTRL_EXT_LINK_MODE_MASK		0x00c00000
 #define	CTRL_EXT_LINK_MODE_GMII		0x00000000
 #define	CTRL_EXT_LINK_MODE_KMRN		0x00000000
 #define	CTRL_EXT_LINK_MODE_1000KX	0x00400000
 #define	CTRL_EXT_LINK_MODE_SGMII	0x00800000
 #define	CTRL_EXT_LINK_MODE_PCIX_SERDES	0x00800000
-#define	CTRL_EXT_LINK_MODE_TBI		0x00C00000
-#define	CTRL_EXT_LINK_MODE_PCIE_SERDES	0x00C00000
+#define	CTRL_EXT_LINK_MODE_TBI		0x00c00000
+#define	CTRL_EXT_LINK_MODE_PCIE_SERDES	0x00c00000
 #define	CTRL_EXT_EIAME		__BIT(24) /* Extended Interrupt Auto Mask En */
 #define CTRL_EXT_I2C_ENA	0x02000000  /* I2C enable */
 #define	CTRL_EXT_DRV_LOAD	0x10000000
@@ -590,8 +590,8 @@ struct livengood_tcpip_ctxdesc {
 #define	FCAL_CONST	0x00c28001	/* Flow Control MAC addr low */
 
 #define	WMREG_FEXTNVM	0x0028	/* Future Extended NVM register */
-#define	FEXTNVM_SW_CONFIG	__BIT(1)
-#define	FEXTNVM_SW_CONFIG_ICH8M	__BIT(27)
+#define	FEXTNVM_SW_CONFIG	__BIT(0)  /* SW PHY Config En (ICH8 B0) */
+#define	FEXTNVM_SW_CONFIG_ICH8M	__BIT(27) /* SW PHY Config En (>= ICH8 B1) */
 
 #define	WMREG_FCAH	0x002c	/* Flow Control Address High */
 #define	FCAH_CONST	0x00000100	/* Flow Control MAC addr high */
@@ -599,8 +599,8 @@ struct livengood_tcpip_ctxdesc {
 #define	WMREG_FCT	0x0030	/* Flow Control Type */
 
 #define	WMREG_KUMCTRLSTA 0x0034	/* MAC-PHY interface - RW */
-#define	KUMCTRLSTA_MASK			0x0000FFFF
-#define	KUMCTRLSTA_OFFSET		0x001F0000
+#define	KUMCTRLSTA_MASK			0x0000ffff
+#define	KUMCTRLSTA_OFFSET		0x001f0000
 #define	KUMCTRLSTA_OFFSET_SHIFT		16
 #define	KUMCTRLSTA_REN			0x00200000
 
@@ -612,8 +612,8 @@ struct livengood_tcpip_ctxdesc {
 #define	KUMCTRLSTA_OFFSET_K1_CONFIG	0x00000007
 #define	KUMCTRLSTA_OFFSET_INB_PARAM	0x00000009
 #define	KUMCTRLSTA_OFFSET_HD_CTRL	0x00000010
-#define	KUMCTRLSTA_OFFSET_M2P_SERDES	0x0000001E
-#define	KUMCTRLSTA_OFFSET_M2P_MODES	0x0000001F
+#define	KUMCTRLSTA_OFFSET_M2P_SERDES	0x0000001e
+#define	KUMCTRLSTA_OFFSET_M2P_MODES	0x0000001f
 
 /* FIFO Control */
 #define	KUMCTRLSTA_FIFO_CTRL_RX_BYPASS	0x0008
@@ -638,7 +638,7 @@ struct livengood_tcpip_ctxdesc {
 #define	KUMCTRLSTA_OPMODE_INBAND_MDIO 0x0004
 
 #define	WMREG_VET	0x0038	/* VLAN Ethertype */
-#define	WMREG_MDPHYA	0x003C	/* PHY address - RW */
+#define	WMREG_MDPHYA	0x003c	/* PHY address - RW */
 
 #define WMREG_FEXTNVM3	0x003c	/* Future Extended NVM 3 */
 #define FEXTNVM3_PHY_CFG_COUNTER_MASK	__BITS(27, 26)
@@ -795,7 +795,7 @@ struct livengood_tcpip_ctxdesc {
 #define	WMREG_OLD_RDBAL0 0x0110	/* Receive Descriptor Base Low (ring 0) */
 #define	WMREG_RDBAL(x) \
 	((x) < 4 ? (0x02800 + ((x) * 0x100)) :	\
-	    (0x0C000 + ((x) * 0x40)))
+	    (0x0c000 + ((x) * 0x40)))
 
 #define	WMREG_OLD_RDBAH0 0x0114	/* Receive Descriptor Base High (ring 0) */
 #define	WMREG_RDBAH(x) \
@@ -826,12 +826,12 @@ struct livengood_tcpip_ctxdesc {
 #define	WMREG_OLD_RDH0	0x0120	/* Receive Descriptor Head (ring 0) */
 #define	WMREG_RDH(x) \
 	((x) < 4 ? (0x02810 + ((x) * 0x100)) :  \
-	    (0x0C010 + ((x) * 0x40)))
+	    (0x0c010 + ((x) * 0x40)))
 
 #define	WMREG_OLD_RDT0	0x0128	/* Receive Descriptor Tail (ring 0) */
 #define	WMREG_RDT(x) \
 	((x) < 4 ? (0x02818 + ((x) * 0x100)) :	\
-	    (0x0C018 + ((x) * 0x40)))
+	    (0x0c018 + ((x) * 0x40)))
 
 #define	WMREG_RXDCTL(x) \
 	((x) < 4 ? (0x02828 + ((x) * 0x100)) :	\
@@ -851,11 +851,11 @@ struct livengood_tcpip_ctxdesc {
 #define	WMREG_OLD_RDH1	0x0148
 #define	WMREG_OLD_RDT1	0x0150
 #define	WMREG_OLD_FCRTH 0x0160	/* Flow Control Rx Threshold Hi (OLD) */
-#define	WMREG_FCRTL	0x2160	/* Flow Control Rx Threshold Lo */
+#define	WMREG_FCRTH	0x2168	/* Flow Control Rx Threhsold Hi */
 #define	FCRTH_DFLT	0x00008000
 
 #define	WMREG_OLD_FCRTL 0x0168	/* Flow Control Rx Threshold Lo (OLD) */
-#define	WMREG_FCRTH	0x2168	/* Flow Control Rx Threhsold Hi */
+#define	WMREG_FCRTL	0x2160	/* Flow Control Rx Threshold Lo */
 #define	FCRTL_DFLT	0x00004000
 #define	FCRTL_XONE	0x80000000	/* Enable XON frame transmission */
 
@@ -898,8 +898,8 @@ struct livengood_tcpip_ctxdesc {
 #define	TX_COLLISION_DISTANCE_FDX	64
 
 #define	WMREG_TCTL_EXT	0x0404	/* Transmit Control Register */
-#define	TCTL_EXT_BST_MASK	0x000003FF /* Backoff Slot Time */
-#define	TCTL_EXT_GCEX_MASK	0x000FFC00 /* Gigabit Carry Extend Padding */
+#define	TCTL_EXT_BST_MASK	0x000003ff /* Backoff Slot Time */
+#define	TCTL_EXT_GCEX_MASK	0x000ffc00 /* Gigabit Carry Extend Padding */
 
 #define	DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
 
@@ -920,27 +920,27 @@ struct livengood_tcpip_ctxdesc {
 #define	WMREG_OLD_TDBAL	0x0420	/* Transmit Descriptor Base Lo */
 #define	WMREG_TDBAL(x) \
 	((x) < 4 ? (0x03800 + ((x) * 0x100)) :	\
-	    (0x0E000 + ((x) * 0x40)))
+	    (0x0e000 + ((x) * 0x40)))
 
 #define	WMREG_OLD_TDBAH	0x0424	/* Transmit Descriptor Base Hi */
 #define	WMREG_TDBAH(x)\
 	((x) < 4 ? (0x03804 + ((x) * 0x100)) :	\
-	    (0x0E004 + ((x) * 0x40)))
+	    (0x0e004 + ((x) * 0x40)))
 
 #define	WMREG_OLD_TDLEN	0x0428	/* Transmit Descriptor Length */
 #define	WMREG_TDLEN(x) \
 	((x) < 4 ? (0x03808 + ((x) * 0x100)) :	\
-	    (0x0E008 + ((x) * 0x40)))
+	    (0x0e008 + ((x) * 0x40)))
 
 #define	WMREG_OLD_TDH	0x0430	/* Transmit Descriptor Head */
 #define	WMREG_TDH(x) \
 	((x) < 4 ? (0x03810 + ((x) * 0x100)) :	\
-	    (0x0E010 + ((x) * 0x40)))
+	    (0x0e010 + ((x) * 0x40)))
 
 #define	WMREG_OLD_TDT	0x0438	/* Transmit Descriptor Tail */
 #define WMREG_TDT(x) \
 	((x) < 4 ? (0x03818 + ((x) * 0x100)) :	\
-	    (0x0E018 + ((x) * 0x40)))
+	    (0x0e018 + ((x) * 0x40)))
 
 #define	WMREG_OLD_TIDV	0x0440	/* Transmit Delay Interrupt Value */
 #define	WMREG_TIDV	0x3820
@@ -986,7 +986,7 @@ struct livengood_tcpip_ctxdesc {
 #define EXTCNFCTR_MDIO_SW_OWNERSHIP	0x00000020
 #define EXTCNFCTR_MDIO_HW_OWNERSHIP	0x00000040
 #define EXTCNFCTR_GATE_PHY_CFG		0x00000080
-#define EXTCNFCTR_EXT_CNF_POINTER	0x0FFF0000
+#define EXTCNFCTR_EXT_CNF_POINTER	0x0fff0000
 
 #define WMREG_EXTCNFSIZE 0x0f08  /* Extended Configuration Size */
 #define EXTCNFSIZE_LENGTH	__BITS(23, 16)
@@ -1066,7 +1066,7 @@ struct livengood_tcpip_ctxdesc {
 #define WMREG_EICS	0x01520  /* Ext. Interrupt Cause Set - WO */
 #define WMREG_EIMS	0x01524  /* Ext. Interrupt Mask Set/Read - RW */
 #define WMREG_EIMC	0x01528  /* Ext. Interrupt Mask Clear - WO */
-#define WMREG_EIAC	0x0152C  /* Ext. Interrupt Auto Clear - RW */
+#define WMREG_EIAC	0x0152c  /* Ext. Interrupt Auto Clear - RW */
 #define WMREG_EIAM	0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
 
 #define WMREG_EICR	0x01580  /* Ext. Interrupt Cause Read - R/clr */
@@ -1083,11 +1083,11 @@ struct livengood_tcpip_ctxdesc {
 #define EITR_COUNTER_MASK_82575	__BITS(31,16)
 #define EITR_CNT_INGR		__BIT(31) /* does not overwrite counter */
 
-#define WMREG_EITR_82574(x)	(0x000E8 + (0x4 * (x)))
+#define WMREG_EITR_82574(x)	(0x000e8 + (0x4 * (x)))
 #define EITR_ITR_INT_MASK_82574	__BITS(15, 0)
 
 #define	WMREG_RXPBS	0x2404	/* Rx Packet Buffer Size  */
-#define RXPBS_SIZE_MASK_82576	0x0000007F
+#define RXPBS_SIZE_MASK_82576	0x0000007f
 
 #define	WMREG_RDFH	0x2410	/* Receive Data FIFO Head */
 #define	WMREG_RDFT	0x2418	/* Receive Data FIFO Tail */
@@ -1494,7 +1494,7 @@ struct livengood_tcpip_ctxdesc {
 #define INVM_MAJOR	__BITS(9,4)
 
 /* Word definitions for ID LED Settings */
-#define ID_LED_RESERVED_FFFF 0xFFFF
+#define ID_LED_RESERVED_FFFF 0xffff
 
 /* ich8 flash control */
 #define ICH_FLASH_COMMAND_TIMEOUT            5000    /* 5000 uSecs - adjusted */
@@ -1530,7 +1530,7 @@ struct livengood_tcpip_ctxdesc {
 #define ICH_FLASH_FRACC    0x0050
 #define ICH_FLASH_FREG0    0x0054
 #define ICH_FLASH_FREG1    0x0058
-#define ICH_FLASH_FREG2    0x005C
+#define ICH_FLASH_FREG2    0x005c
 #define ICH_FLASH_FREG3    0x0060
 #define ICH_FLASH_FPR0     0x0074
 #define ICH_FLASH_FPR1     0x0078
@@ -1540,10 +1540,10 @@ struct livengood_tcpip_ctxdesc {
 #define ICH_FLASH_OPTYPE   0x0096
 #define ICH_FLASH_OPMENU   0x0098
 
-#define ICH_FLASH_REG_MAPSIZE      0x00A0
+#define ICH_FLASH_REG_MAPSIZE      0x00a0
 #define ICH_FLASH_SECTOR_SIZE      4096
-#define ICH_GFPREG_BASE_MASK       0x1FFF
-#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
+#define ICH_GFPREG_BASE_MASK       0x1fff
+#define ICH_FLASH_LINEAR_ADDR_MASK 0x00ffffff
 
 #define ICH_NVM_SIG_WORD	0x13
 #define ICH_NVM_SIG_MASK	0xc000

Index: src/sys/dev/pci/if_wmvar.h
diff -u src/sys/dev/pci/if_wmvar.h:1.33.6.1 src/sys/dev/pci/if_wmvar.h:1.33.6.2
--- src/sys/dev/pci/if_wmvar.h:1.33.6.1	Tue Aug  1 23:33:18 2017
+++ src/sys/dev/pci/if_wmvar.h	Mon Apr 16 14:25:49 2018
@@ -1,4 +1,4 @@
-/*	$NetBSD: if_wmvar.h,v 1.33.6.1 2017/08/01 23:33:18 snj Exp $	*/
+/*	$NetBSD: if_wmvar.h,v 1.33.6.2 2018/04/16 14:25:49 martin Exp $	*/
 
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -117,7 +117,7 @@
  *  |  |  |  |  +---------- 82571 - 82572 - 82573 - 82574 - 82583
  *  |  |  |  |  |  +--------- 82575 - 82576 - 82580 - I350 - I354 - I210 - I211
  *  |  |  |  |  |  |  +-- 80003
- *  |  |  |  |  |  |  |  +-- ICH8 - ICH9 - ICH10 - PCH - PCH2 - PCH_LPT
+ *  |  |  |  |  |  |  |  +-- ICH8 - 9 - 10 - PCH - 2 - LPT - SPT - CNP
  *  |  |  |  |  |  |  |  |
  * -+--+--+--+--+--+--+--+----------------------------------------------->
  */
@@ -157,6 +157,7 @@ typedef enum {
 	WM_T_PCH2,			/* PCH2 LAN */
 	WM_T_PCH_LPT,			/* PCH "Lynx Point" LAN (I217, I218) */
 	WM_T_PCH_SPT,			/* PCH "Sunrise Point" LAN (I219) */
+	WM_T_PCH_CNP,			/* (I219) */
 } wm_chip_type;
 
 typedef enum {

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