Module Name: src Committed By: simonb Date: Thu May 7 11:43:28 UTC 2020
Modified Files: src/sys/arch/mips/include: cpuregs.h Log Message: Add PRID definition for newer SiByte SB1 cores (rev 0x11). Add a constant for SiByte/BCRM cacheable coherent TLB cache attribute. To generate a diff of this commit: cvs rdiff -u -r1.96 -r1.97 src/sys/arch/mips/include/cpuregs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.