Module Name: src Committed By: simonb Date: Sun Jun 14 12:58:01 UTC 2020
Modified Files: src/sys/arch/mips/mips: cache.c Log Message: Support Octeon Cavium cnMIPS I, II and III cores that have various non-standard cache configurations (in terms of following MIPS spec for defining cache configurations). Move (most) Octeon support into a single place. To generate a diff of this commit: cvs rdiff -u -r1.65 -r1.66 src/sys/arch/mips/mips/cache.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.