Module Name: src
Committed By: martin
Date: Mon Jul 13 13:33:29 UTC 2020
Modified Files:
src/sys/arch/x86/include [netbsd-9]: specialreg.h
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #998):
sys/arch/x86/include/specialreg.h: revision 1.162
sys/arch/x86/include/specialreg.h: revision 1.164
sys/arch/x86/include/specialreg.h: revision 1.165
sys/arch/x86/include/specialreg.h: revision 1.166
sys/arch/x86/include/specialreg.h: revision 1.167
sys/arch/x86/include/specialreg.h: revision 1.168
- AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL".
- Add some bit definitions of AMD's CPUID Fn8000_001f Encrypted Memory
features.
- Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept bit.
- Modify comment.
Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE.
This bit makes lfence instruction serializing.
Add some definitions from the latest Intel SDM plus small fix:
- Add CPUID leaf 6 %eax bit 19 for HW_FEEDBACK* and IA32_PACKAGE_TERM* MSRs.
- Add CPUID leaf 7 %ecx bit 31 for Protection Keys.
- Add definition of Load only TLB and Store only TLB.
- Add IF_PSCHANGE_MC_NO bit of IA32_ARCH_CAPABILITIES
- Fix HWP_IGNIDL.
Add SRBDS_CTRL bit.
style and fix typo
To generate a diff of this commit:
cvs rdiff -u -r1.150.2.6 -r1.150.2.7 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
