Module Name: src Committed By: matt Date: Thu Jun 20 05:29:01 UTC 2013
Modified Files:
src/sys/arch/arm/cortex: a9_mpsubr.S
Log Message:
Set caching bits on the TTBR for ARMv7
Make sure TTCR is 0
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/a9_mpsubr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
