Module Name: src Committed By: martin Date: Tue Jul 4 14:35:21 UTC 2017
Modified Files: src/sys/dev/pci [netbsd-8]: pci_subr.c pcireg.h Log Message: Pull up following revision(s) (requested by msaitoh in ticket #80): sys/dev/pci/pci_subr.c: revision 1.184 sys/dev/pci/pci_subr.c: revision 1.185 sys/dev/pci/pci_subr.c: revision 1.186 sys/dev/pci/pci_subr.c: revision 1.187 sys/dev/pci/pci_subr.c: revision 1.188 sys/dev/pci/pci_subr.c: revision 1.189 sys/dev/pci/pcireg.h: revision 1.131 Add missing return to print the Slot Power Limit Value correctly. Fix to print the following bit fields correctly. - Supported Link Speeds Vector in LCAP2 - Lower SKP OS Generation Supported Speed Vector in LCAP2 - Lower SKP OS Reception Supported Speed Vector in LCAP2 - Enable Lower SKP OS Generation Vector in LCTL3 Note that the above bitfields start from 0 and the follwing bitfields start from 1: - Maximum Link Speed in LCAP - Current Link Speed in LCSR - Target Link Speed in LCSR2 For the Target Link Speed in LCSR2, 0 is allowed for a device which supports 2.5GT/s only (and this check also works for devices which compliant to versions of the base specification prior to 3.0. Tested with BCM5709: - Target Link Speed: unknown value (0) + Target Link Speed: 2.5GT/s For Attention Indicator Control bit and Power Indicator Control bit, it's allowed to be a read only value 0 if corresponding capability register bit is 0. Fix a bug that LTR's latency in L1 PM Substates capability and Latency Tolerance Reporting capability isn't printed correctly. Fix printf format/argument. To generate a diff of this commit: cvs rdiff -u -r1.183 -r1.183.2.1 src/sys/dev/pci/pci_subr.c cvs rdiff -u -r1.130 -r1.130.2.1 src/sys/dev/pci/pcireg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.