Module Name: src
Committed By: maya
Date: Tue Aug 8 09:33:41 UTC 2017
In working around loongson errata clear BTB and RAS, same as
other operating systems.
15 Errata: Issue of Out-of-order in loongson (translated)
In loongson 2F, because of the branch prediction, sometimes the CPU
may fetch the instructions from some unexpected area (for example I/O
space). It is an invalid operation. There are two ways for the CPU to
choose the branch target. The first one is predicting the branch
target according to the branch target history. The second one is
calculating the branch target by the ALU. There are most 8
instructions in the instruction window at the same time in loongson2f
(Remember the loongson 2f is superscalar, right?). Hence, the
branch target of an indirect branch(such as jr) could be got(may be
predicted by the branch target history) earlier and the instrctions of
the branch target could be prefetched even if there are branch
instructions before it. As a result, it is possible to fetch the
instructions from I/O region( say out-of the physical address range of
[0- 0x100000]) in kernel model because of the instruction prefetch of
the branch target.
There are some suggestions to prevent prefetching instructions from
the I/O region in kernel mode.
(1) When switching from user model to kernel model, you should flush
the branch target history such as BTB and RAS.
(2) Doing some tricks to the indirect branch target to make sure that
the indirect branch target can not be in the I/O region.
To generate a diff of this commit:
cvs rdiff -u -r1.100 -r1.101 src/sys/arch/mips/mips/mipsX_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.