Module Name:    src
Committed By:   msaitoh
Date:           Mon Mar 12 06:20:33 UTC 2018

Modified Files:
        src/sys/arch/x86/include: cacheinfo.h

Log Message:
 Add 3way and 6way of L2 cache or TLB on AMD CPU.

To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/x86/include/cacheinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

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