Module Name:    src
Committed By:   bouyer
Date:           Wed Apr  4 16:01:05 UTC 2018

Modified Files:
        src/sys/arch/arm/sunxi: sunxi_tcon.c

Log Message:
Reset more regs at attach time, just in case.
As the mux is in unit 0 but is used by both units, we have to keep
  unit 0's ahb clock enabled.
Properly set sc_output_type.

Now pipeline 1 can be activated without activating pipeline 0 first.

To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/sunxi/sunxi_tcon.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

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