CVSROOT: /cvs Module name: src Changes by: [email protected] 2019/03/16 23:25:06
Modified files:
sys/arch/octeon/dev: octcib.c octcit.c octciu.c octeon_intr.c
sys/arch/octeon/include: intr.h
Log message:
Let each interrupt controller driver choose how to implement
intr_barrier(9).
With this change, the barrier should finally work properly with
cnmac(4) interrupts that have been assigned to secondary cores.
