CVSROOT: /cvs Module name: src Changes by: kette...@cvs.openbsd.org 2019/08/18 09:51:18
Modified files:
sys/dev/ic : dwiic.c
Log message:
In polled mode, wait on STOP detected bit to be set in the interrupt status
register like we do for non-polled mode. This seems to increase the
reliability of i2c transfers on the controller integrated on the Ampare
eMAG processor.
ok jcs@, mlarkin@
