On Thu, Oct 31, 2019 at 04:39:37PM -0600, Theo de Raadt wrote:
> There are only three hard problems in computer science: Cache
> invalidation, naming things, and off-by-one errors.
>
> This was a two-in-one.
I managed to create a reproducable case by studying a DNS failure that
involved a particular sized UDP packet. So the naming thing was
involved as well :-)
-Otto
>
> Patrick Wildt <[email protected]> wrote:
>
> > CVSROOT: /cvs
> > Module name: src
> > Changes by: [email protected] 2019/10/31 16:28:26
> >
> > Modified files:
> > sys/arch/arm/arm: cpufunc_asm_armv7.S
> >
> > Log message:
> > In 2013, when OpenBSD/armv7 was still rather early, improvements for
> > that platform have been trickling in bit by bit. One of those
> > changes unfortunately introduced a regression in cache flushes. The
> > check for the length in the cache-flush-loop was changed from the
> > instruction bpl to bhi. This has the effect that it does not branch
> > on zero anymore. Due to the length decrement at the beginning of
> > the function, which was not removed, a length of (n * cacheline) + 1
> > means that the loop misses one run! This means it is possible that
> > the last byte of a DMA transfer was incorrect, as one could see on
> > network packets often enough. Remove that instruction, which makes
> > it even more similar to the OpenBSD/arm64 code.
> >
> > ok deraadt@
> >
>
