CVSROOT: /cvs Module name: src Changes by: m...@cvs.openbsd.org 2009/10/22 14:10:46
Modified files:
sys/arch/mips64/mips64: interrupt.c trap.c
sys/arch/sgi/include: intr.h
sys/arch/sgi/localbus: macebus.c
Log message:
unifdef -DIMASK_EXTERNAL to the mips code. Support for interrupt masking at
coprocessor 0 sr level might come back in the future if hardware support
requires it, but at the moment it's getting in the way of larger changes.
``In the Attic, noone can hear you scream''
