CVSROOT: /cvs Module name: src Changes by: [email protected] 2021/06/17 06:55:38
Modified files:
regress/lib/libc/ieeefp/except: Makefile
regress/lib/libc/setjmp-fpu: fpu.c setjmp-fpu.c
regress/lib/libm/fenv: fenv.c
regress/lib/libm/msun: fenv_test.c
Log message:
Like ARM, RISC-V does not implement floating point exceptions.
