CVSROOT: /cvs
Module name: src
Changes by: [email protected] 2023/07/09 13:11:30
Modified files:
sys/dev/fdt : rkpciephy.c
Log message:
It turns out that there are seperate pins for the PCIe Gen 2 and 3, which
means that the x4 PCIe controller can get all PCIe Gen 3 lines, while the
others then only get PCIe Gen 2 lines. Therefore the decision on how to
configure the mux needs to be adjusted so that the PCIe Gen 3 lines are
only routed to other PCIe controllers when they are explicitly configured
for them. While there, fix an obvious typo.
ok kettenis@
