CVSROOT: /cvs
Module name: src
Changes by: [email protected] 2024/04/07 15:08:59
Modified files:
sys/arch/riscv64/dev: mainbus.c simplebus.c
Log message:
The RISC-V architecture has cache-coherent DMA... until it doesn't. This
is indicated by a "dma-noncoherent" property on the bus or device nodes
in the device tree. Set the BUS_DMA_COHERENT flag on the DMA tag for
mainbus(4) and modify the flags based on the presence of "dma-coherent"
and "dma-noncoherent" properties where appropriate.
ok patrick@
