CVSROOT: /cvs
Module name: src
Changes by: [email protected] 2010/06/07 17:35:24
Modified files:
sys/dev/pci : auich.c
Log message:
Fix various problems of auich on SiS 7012 based chips:
- rework auich_halt_pipe() and use it to ensure AUICH_RR is
set only after DMA is halted (spec says to do so)
- rework auich_calibrate(): clear interrupt and event bits in
AUICH_STS and ensure CIV counter is not changed.
- in the interrupt handler, set LVI to (qptr - 1) rather than
the max value (bug introduced by previous commit)
All fixes are from Christopher Zimmermann <madroach at zakweb.de>,
Thanks!
tested on two different intel-based auich devices,
ok jakemsr
