CVSROOT: /cvs Module name: src Changes by: m...@cvs.openbsd.org 2012/04/05 15:48:37
Modified files:
sys/arch/sgi/hpc: zs.c
Log message:
Lower ZS_DELAY() back to what it was, but issue a bus_space_barrier() after
every register write. Hinted by IRIX' <sys/z8530.h>.
While there, flip the CTS, DCD, RTS and DTR bits in registers #0 and #5.
Aforementioned header says they are inverted due to a hardware bug.
Tested on IP20, IP22 and IP24.
