CVSROOT: /cvs Module name: src Changes by: [email protected] 2014/02/18 06:47:53
Modified files:
sys/arch/amd64/stand/libsa: random_i386.S
sys/arch/i386/stand/libsa: random_i386.S
Log message:
Actually check to see if the CPU supports tsc, rather than assuming that
it does and triggering an illegal instruction trap when it does not.
Found the hard way and fix tested by nick@
