CVSROOT: /cvs
Module name: src
Changes by: [email protected] 2014/09/06 04:15:52
Modified files:
sys/arch/macppc/macppc: cpu.c genassym.cf locore.S
sys/arch/powerpc/include: cpu.h
sys/arch/powerpc/powerpc: cpu_subr.c
sys/arch/socppc/socppc: cpu.c genassym.cf locore.S
Log message:
Rewrite cpu_idle & friends to not check and update the hid0 register
in the idle loop, in preparation for G5 support.
Only do a disable/enable interrupt dance if the running CPU supports a
sleep mode.
Fix entering ddb(8) from interrupt context by not modifying the return
address of the 'forced' trap frame.
While here, modify the existing logic to terminate prefetching of all
data streams if AltiVec is supported before setting the POW bit.
With inputs/explanations from drahn, looks ok to miod@
