CVSROOT: /cvs
Module name: src
Changes by: [email protected] 2015/12/08 22:17:44
Modified files:
sys/dev/pci/drm: i915_pciids.h
sys/dev/pci/drm/i915: i915_drv.h intel_dp.c intel_drv.h
Log message:
Backport some commits from mainline linux to enable High Bit Rate 2
(HBR2) for Broadwell and non-ULX Haswell DisplayPort. This enables
support for 3840x2160 60Hz SST.
Initial patch from and tested by Scot Doyle.
drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable devices
from Todd Previte
06ea66b6bb445043dc25a9626254d5c130093199
drm/i915: don't try DP_LINK_BW_5_4 on HSW ULX
from Paulo Zanoni
9bbfd20abe5025adbb0ac75160bd2e41158a9e83
drm/i915/dp: add missing \n in the TPS3 debug message
from Jani Nikula
f8d8a672f9370278ae2c9752ad3021662dbc42fd
drm/i915/dp: only use training pattern 3 on platforms that support it
from Jani Nikula
7809a61176b385ebb3299ea43c58b1bb31ffb8c0
