CVSROOT: /cvs
Module name: src
Changes by: [email protected] 2016/08/14 02:23:52
Modified files:
sys/arch/mips64/include: cpu.h mips_cpu.h pte.h
sys/arch/mips64/mips64: context.S db_machdep.c mips64r2.S pmap.c
tlbhandler.S trap.c
sys/arch/octeon/octeon: locore.S machdep.c
Log message:
Utilize the TLB Execute-Inhibit bit with non-executable mappings on CPUs
that support the Execute-Inhibit exception. This makes user space W^X
effective on Octeon Plus and later Octeon versions.
Feedback from miod@, thanks!
No objection from deraadt@
