CVSROOT: /cvs
Module name: src
Changes by: [email protected] 2017/02/05 05:59:32
Modified files:
sys/arch/arm64/arm64: pmap.c
Log message:
As far as we understood the architecture reference manual it should
only need a data cache write-back to PoU (Point of Unification) to
make changes to the pagetables visible. Interestingly enough, this
does not seem to work on the AMD hardware. Instead we need to flush
to PoC (Point of Coherence), which essentially means flush to memory.
Surprisingly even FreeBSD flushes their pagetable changes to PoC, and
they have done that since the code was first imported. Until we find
out whether this is a software bug or just completely expected, switch
us to flushing to PoC as well. This makes my AMD machine behave.
