CVSROOT: /cvs
Module name: src
Changes by: v...@cvs.openbsd.org 2018/02/24 04:42:31
Modified files:
sys/arch/loongson/dev: bonito.c
sys/arch/loongson/loongson: generic2e_machdep.c isa_machdep.c
loongson3_intr.c yeeloong_machdep.c
sys/arch/mips64/include: cpu.h
sys/arch/mips64/mips64: interrupt.c
sys/arch/octeon/dev: octcit.c octciu.c
sys/arch/sgi/localbus: int.c macebus.c
sys/arch/sgi/sgi: intr_template.c ip27_machdep.c
sys/arch/sgi/xbow: xheart.c
Log message:
Declare ci_ipl volatile to prevent the compiler from optimizing
or reordering accesses to the variable. Assume that the assembler
preserves the correct sequence of instructions, which allows the
removal of the explicit noreorder/reorder toggles from the C code.
With ci_ipl being volatile, drop mips_sync() calls that follow
the accesses of the variable. The sync is redundant as a compiler
barrier. In addition, the MIPS64 CPU designs should not need the
sync for pipeline or write buffer control. According to miod@,
the use of the instruction is a carryover from code targeting
early MIPS designs that lack tight integration with the cache
and write buffer.
Discussed with and testing help from miod@.
Tested on CN5020, CN6120, CN7130, CN7360, Loongson 2F and 3A1000,
R4400, R8000, R10000 and R16000.
