On Wed, 13 Apr 2005 11:26:33 +0200 "Konrad Eisele" <[EMAIL PROTECTED]> wrote:
> "David S. Miller" <[EMAIL PROTECTED]> schrieb am 12.04.05 21:28:47: > > > > On Tue, 12 Apr 2005 14:50:54 +0200 > > "Konrad Eisele" <[EMAIL PROTECTED]> wrote: > > > > > I trying to get sparc32-smp run on a Leon3 sparc, > > > it uses a virtually indexed/tagged cache. Is it possible > > > to run smp on such a processor? > > > > Yes, it's just painful. Model your cache flushing on the > > sun4c code. > > - > > It's difficult to understand how smp works when cache coherency isn't > done by hardware. Oh nevermind, yes that is next to impossible. If the cpus aren't doing any cache coherency protocol on the system bus, you're basically out of luck. I forgot that physical indexing was necessary for a cache coherency protocol since the system bus works with physical addresses. - To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
