On 8/12/07, David Miller <[EMAIL PROTECTED]> wrote: > > Specifically, how are the interrupts routed, which interrupts (ZS, > > ESP, Lance, timers, floppy, cgthree) go through the interrupt > > controller? > > There is no interrupt controller, the individual devices and > SBUS slot interrupt sources are wired up directly to the cpu.
Then what device is poked by arch/sparc/kernel/sun4c_irq.c, I thought this was the controller? Thanks for the other information. Implementing the MMU is going to be difficult. - To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
