On Wednesday 20 February 2008 21:27, Robert Schwebel wrote:
> On Tue, Feb 19, 2008 at 10:49:42AM +0100, Andrea Paterniani wrote:
> > Subject: [patch-2.6.25-rc2-spi_imx] arm: SPI controller driver for
> > Freescale iMX From: Andrea Paterniani <[EMAIL PROTECTED]>
> >
> > Kernel version: linux-2.6.25-rc2.
> > Patch description:
> > 1) Some comments changed and/or added.
> > 2) End of transfers is now managed on TXFIFO empty interrupt after the
> > last write to TXFIFO. This management shorten interrupt execution time
> > removing the waiting for TXFIFO emptying.
> > On TXFIFO empty interrupt the handler needs only to wait for the end
> > of ongoing transaction (polling SPI_CONTROL_XCH) to close transfer. 2.1)
> > Write only transfers are closed flushing RXFIFO.
> > 2.2) Read transfers are closed reading trailing bytes from RXFIFO.
> > 2.3) Read transfers where RXFIFO overrun occurred are closed flushing
> > RXFIFO and aborting message.
> > 3) Fifos are now flushed via SPI disable after the end of ongoing
> > transaction.
>
> How different is the i.MX1 SPI driver from our combined i.MX27/i.MX21
> driver?
Both SPI implementations differ in hardware.
Register i.MX1 i.MX2
RxData: 16 bit 32 bit
TxData: 16 bit 32 bit
ControlReg: 16 bit 32 Bit plus additional control bits
IntReg 16 bit 32 Bit plus additional status/control bits,
some are shifted to other bit positions
than i.MX1
TestReg 16 bit 16 bit, but additional control bits
PeriodReg same
DMAreg seems the same
ResetReg same
It would be nice of we could handle both hardware implementations with one
driver.
Juergen
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