"Janesh Ramakrishnan" <[EMAIL PROTECTED]> wrote:
> Thanks for your insightful clarifications. They really helped. A bit of 
> commenting in this part of the code might save others from bugging you like I 
> did :) Just a suggestion. 

Yes, should probably do that...at least use the DIV_ROUND_UP() macro
since open-coding it makes the code look more cryptic than it really is.

The patch below should improve things, and fix a minor bug.

Haavard

=================[cut here]====================

>From 0c6a4d5c12f302b4a3a88c0a38fb34ad77309dc0 Mon Sep 17 00:00:00 2001
From: Haavard Skinnemoen <[EMAIL PROTECTED]>
Date: Tue, 29 Apr 2008 10:20:10 +0200
Subject: [PATCH] atmel_spi: Clean up baud rate divisor calculation

Make the baud rate divisor calculation code a bit more readable and
add a few comments.

Also fix wrong debug information being displayed when !new_1 and
max_speed_hz == 0.

Signed-off-by: Haavard Skinnemoen <[EMAIL PROTECTED]>
---
 drivers/spi/atmel_spi.c |   26 +++++++++++++++++++-------
 1 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index 02c8e30..91bfd5c 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -536,14 +536,25 @@ static int atmel_spi_setup(struct spi_device *spi)
                return -EINVAL;
        }
 
-       /* speed zero convention is used by some upper layers */
+       /*
+        * Pre-new_1 chips start out at half the peripheral
+        * bus speed.
+        */
        bus_hz = clk_get_rate(as->clk);
+       if (!as->new_1)
+               bus_hz /= 2;
+
        if (spi->max_speed_hz) {
-               /* assume div32/fdiv/mbz == 0 */
-               if (!as->new_1)
-                       bus_hz /= 2;
-               scbr = ((bus_hz + spi->max_speed_hz - 1)
-                       / spi->max_speed_hz);
+               /*
+                * Calculate the lowest divider that satisfies the
+                * constraint, assuming div32/fdiv/mbz == 0.
+                */
+               scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
+
+               /*
+                * If the resulting divider doesn't fit into the
+                * register bitfield, we can't satisfy the constraint.
+                */
                if (scbr >= (1 << SPI_SCBR_SIZE)) {
                        dev_dbg(&spi->dev,
                                "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
@@ -551,8 +562,8 @@ static int atmel_spi_setup(struct spi_device *spi)
                        return -EINVAL;
                }
        } else
+               /* speed zero means "as slow as possible" */
                scbr = 0xff;
-       sck_hz = bus_hz / scbr;
 
        csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
        if (spi->mode & SPI_CPOL)
@@ -587,6 +598,7 @@ static int atmel_spi_setup(struct spi_device *spi)
                spin_unlock_irqrestore(&as->lock, flags);
        }
 
+       sck_hz = bus_hz / scbr;
        dev_dbg(&spi->dev,
                "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
                sck_hz, bits, spi->mode, spi->chip_select, csr);
-- 
1.5.4.3


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