Long ago, I posted a message on linux-arm-kernel describing data corruption that I was seeing on PXA270 SSP transfers using DMA: http://marc.info/?l=linux-arm-kernel&m=117780219128682&w=2
I have recently upgraded to Kernel 2.6.27.4 and am now using the IOCTL interface provided by spidev ... and unfortunately am still seeing data corruption with DMA transfers. I have a user program that is sending single blocks (1-255 words) of fabricated, non-zero data to an outbound processor (at 300 kHz). I find that after a small number of blocks (10-20), the outboard processor will receive a packet that begins with multiple zeros, rather than the intended data. I have put printk statements into spidev that show that the correct, non-zero data is always present in the DMA bounce buffer before and after the transfer - even on the packets that fail to arrive. If I display the DMA flag in the platform data, then the transfers continue indefinitely without any problems. More interestingly, while using DMA, if I simply insert a sched_yield (on an otherwise unoccupied processor), before each transfer from user land, the problem disappears ! In my original posting last year, I suspected a cache coherency problem. However, based on the latest symptoms, I'm wondering if the SSP transfer might be initiated before the DMA controller is ready/able to provide source data .... Thanks, Scott. ------------------------------------------------------------------------- This SF.Net email is sponsored by the Moblin Your Move Developer's challenge Build the coolest Linux based applications with Moblin SDK & win great prizes Grand prize is a trip for two to an Open Source event anywhere in the world http://moblin-contest.org/redirect.php?banner_id=100&url=/ _______________________________________________ spi-devel-general mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/spi-devel-general
