Hi,
I have found a race condition in the PSC driver for the MPC5200.
The effect is that the processor let the RXFIFO interrupt pending and
the interrupt handler is called as soon as the IRQ is enabled again, not
after receiving the number of bytes set with the FIFO Alarm (~400).
In fact:
recv_at_once = in_be16(&fifo->rfnum);
^---RFNUM is read only once
[...]
if (rx_buf) {
for (; recv_at_once; rb++, recv_at_once--)
[FIFO wird gelesen] <-- now further bytes are coming
Enabling the traces, I can check that the driver writes only 20-30 Bytes
into the FIFO instead of 400 as set by the Alarm.
Because the FIFO does not become empty, according to the MPC5200 manual
the RXRDY/FFULL interrupt is not removed and a new interrupt is
generated at the next iteration.
This causes a lot of interrupts, much more as expected, generating an
higher CPU load as the usage of the RXFIFO really requires.
I will send a patch for review in short time to fix this issue.
Stefano
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