2009/8/17 H Hartley Sweeten <[email protected]>: > My question is, if a message is composed of multiple transfers, is it possible > for the speed to change mid message? If it is, does this need to be handled?
Typically your SPI HW is clocked by some on-chip clock line, and then the SPI speed is derived from this clock line by a simple counter/divider register that you set up. So if that clock line coming in from the outside can change frequency in the middle of the message this can of course happen. The divided speed will change proportionally at that point.. So if you want full control you also need to hook into the clk framework if you have SW control over your platforms clocks, then add some prechange and postchange notifiers for clock speed change and make sure you don't exit the prechange in the middle of a message and not process a new one until after the postchange has completed. There is nothing like that in the generic clk framework right now to help you unfortunately, I've been thinking a bit about it. Linus Walleij ------------------------------------------------------------------------------ Let Crystal Reports handle the reporting - Free Crystal Reports 2008 30-Day trial. Simplify your report design, integration and deployment - and focus on what you do best, core application coding. Discover what's new with Crystal Reports now. http://p.sf.net/sfu/bobj-july _______________________________________________ spi-devel-general mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/spi-devel-general
